SPI interrupt too slow for SPI frequency

[Gpeti]

I need to confirm my understanding.

Say that my STM32H7 SPI is setup as Slave and that it processes the incoming SPI data byte per byte in interruption.

It is very likely to happen that the SPI throughput is faster than the SPI interrupt handler duration: I measured (roughly) the duration of my SPI handler as being 140 cycles or 300ns for my clock setup.

Do you confirm that the bytes are not lost as long as the reception FIFO is not full ? In my example I always receive 5 bytes commands from the Master so I should never lose bytes due to this issue. Is it correct ?

PS: I know there are faster ways to process incoming data than byte per byte: using DMA or 32 bits data frame.

[TDK · Accepted solution]

> Do you confirm that the bytes are not lost as long as the reception FIFO is not full?

That is correct. If more bytes arrive while you're in the ISR, they just get added to the FIFO, and likely your ISR will be called immediately again when it finishes depending on your settings.