SPI Data Register problem in Slave!

[ho2]

Posted on January 23, 2016 at 08:30

Hello everyone

Recently I connect two STM32F401RE Nucleo with SPI interface.The configurations for master and slave are full duplex, CLK/256, 16-bit, Mode 0 and MSB first. When master produce the clock, data (0x0080) from slave will send out to master, but after some transitions slave data will slightly shift to the left(0x0100) and again after some transitions data will become 0x0200 and so on. I disconnect MOSI pin and connect Slave MOSI pin to gnd and test the data, it happend again. I used logic analyzer and Keil debugger, both confirmed that the data has been changed. Something will change the Slave SPI Data register and I can't completely clear it before sending the rest of data. Did anyone experience same problem?

[ho2]

Posted on January 24, 2016 at 13:09It's me again. I had some researches and tests. I understand when this problem happens BSY flag in SPI1 stays high and I can't cleared it. So I think, I need a safe procedure to send data by slave without getting any SPI1 error or at least if any error happened I'll be able to clear it before sending next data. Can anyone help?