SPI Bus Impedance

[Albi G.]

Hi guys, i am going to connect 2 STM32 via 3 SPI busses for high speed data transfer throughput (STM32H7 <-> STM32G4).

The STM32G4 will be Master and the SCLK-frequency will be 84MHz - i will use the associated pins in the highest speed mode setting.

I am having an extremely hard time to find any information about layout guidelines for the SPI-Busses in general. Same is true for the MCO-output.

Are there any recommendations which trace impedance to aim for? If possible i like to avoid series resistors for the SPI-Lines - people seem to include those via trial and error or because of good faith... thats not engineering in my mind.

I dont have very long traces (60mm) but i have EMI-sensitive circuitry on board.

Thank you.

[TDK]

> Do you now understand the benefit of even a partial source matching?

I understand the theoretical argument. My argument is one of practicality--that it is very likely impedance matching is not needed.

The range of trace impedances you can achieve is not very large. If you ignore the problem, your trace will still have an impedance within this practical range. You can read a book on it, or you can hook it up on the bench, measure the signal, and let your decision be guided by those results.

JW makes a good argument below.

[RMcCa]

From what i can gleen from the h7 rm and datasheet, you want to use the lowest port speed you can to minimize the emi and ringing because the port speed controls the slew rate?

What about the I/O compensation cell? The rm is really sketchy on the subject.​

[S.Ma]

Focus on the ground loop with single ended signals. Termination built-in pull-down resistor and slew rate control are other tuning knobs to play with.