Confusion about PA impedance specification of STM32WL31xx

[Franz.1]

Hi!

If I look at the datasheet of STM32WL31xx, I find Table 34. PA impedance which tells e.g. an optimum load impedance of 32 Ω // 16 nH in line 5 (high power, 868MHz)

This STM32WL31xx is (according to the datasheet) available in VFQFPN32 and VFQFPN48 packages.

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Now, while reading the AN5457 (RF matching network design guide for STM32WL Series), I get confused. This AN should cover the whole STM32WL31 and STM32WL33 series , right? So It should definitely be valid for my STM32WL31K8 in VFQFPN32 pakage?

Now to my questions:

1.) If the AN5457 is applicable, why does PA matching impedance measurements in Appendix A not contain any PA impedance measurements for the VFQFPN32 package?

2.) If I compare the datasheet PA load impedance given at the top of this post with the "next best" data of the UFQFPN48 package, the values are not anywhere near that of the values in the datasheet.

Can anyone tell which impedance value I should use as a starting point for calculating the matching network (for HP_TX @ 868MHz)?

Thanks

[Saverio GRUTTA]

Hello

The AN5457 covers only the STM32WL5 series and does not include the STM32WL3x series. For the STM32WL31 in the HP_TX @ 868 MHz configuration, I recommend referring to the matching network used in the reference design

STDES-WL3C4SMH: 4-Layer Reference design based on SMDs with STM32WL3 QFN48 SoC - 868 MHz - 16 dBm https://www.st.com/en/evaluation-tools/stdes-wl3c4sMh.html#overview

Best regards

Saverio

[Franz.1]

Hi @Saverio GRUTTA !

Thanks for the clarification regarding the AN5457. (I have to point out that it could be documented more clearly, because when the appnotes talks about the STM32WL, I would assume as a user that the STM32WL3x is part as well as STM32WL5x) =)

Anyway: I also found the https://www.st.com/resource/en/data_brief/stdes-wl3c2sll.pdf

Can you be so kind to clarify some more things for me:

1.) I see the 4-Layer STDES-WL3C4SMH as well as the 2-Layer STDES-WL3C2SMH design. Since I am not sure If I need to go with a 4L design (rest of the PCB will be rather simple) : What is the benefit of the 4L reference design compared to the 2L variant?

2.) Can you suggest or recommend a chip antenna to be used with those reference designs?

3.) Since there is no reference design for the VFQFPN32 package, I assume I could use the same values of the BOM as in the VFQFPN48 reference designs?

Thank you so much!

[Saverio GRUTTA · Accepted solution]

Hello,

We will release a new revision of AN5457 specifying that the document is only applicable to the WL5 series and not to the WL3 series.

1)Using the STDES-WL3C2SMH (2 layers PCB) increases power consumption by approximately 4 mA to achieve 16 dBm output, and sensitivity degrades by about 1 dB.

2) Sorry, but we have not yet validated any reference design with a chip antenna.

Yes I confirm the same BOM for both the packages.

Best regards

Saverio