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zhiyongwoo
zhiyongwoo
Associate III
May 17, 2020
Question

Speed different when accessing Peripheral Register (i.e. GPIOx_IDR) vs using DMA to copy GPIOx_IDR to SRAM?

  • May 17, 2020
  • 3 replies
  • 1112 views

Hi Experts,

May I know is there any speed different between access direct to Peripheral Register like, GPIOx_IDR? with access directly to SRAM ( using DMA to do Peripheral to Memory)?

0693W000001cOCuQAM.png

From this block diagram, the GPIOx_IDR is using AHB1 bus and it runs at 180MHz which is same max speed on my system clock freq.

Does this mean, I have the same speed when accessing into Peripheral GPIOx register vs SRAM? Any latency when accessing to Peripheral GPIOx ? Do I need to wait for the GPIOx clock to sync and so on?

This topic has been closed for replies.

3 replies

waclawek.jan
waclawek.jan
Super User
May 17, 2020

What exactly do you mean by "speed" here? One word moves from GPIO_IDR to target (DMA input or processor input) mostly within one cycle, but the latencies (i.e. time from some stimulus until the transfer actually happens) and thus a sustained flow when the request is repeated, depends on many factors and may be (maybe surprisingly) lower with reading from processor than when reading using DMA.

Read AN4031.

JW

zhiyongwoo
zhiyongwooAuthor
Associate III
May 17, 2020

My main concern here is, I do not want to wait for any delay to read the GPIOx IDR value. That is why I was thinking to use DMA to do the P2M transfer while I have my code running in "Parallel". But do I have latency delay when accessing to variable store in SRAM?

From the block diagram, it seems like SRAM and GPIOx are running at the same bus line with the same max freq. Does that mean the use of DMA is unnecessary?

waclawek.jan
waclawek.jan
Super User
May 17, 2020

> I do not want to wait for any delay to read the GPIOx IDR value.

GPIO is on a similar AHB bus than SRAM, so it's probably the same access time.

JW

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