Simple Multicore Core to Core Communication with STM32H7

[JR1]

Hello Team,

how can a simple core to core communication on the STM32H7 be implemented? We want to exchange 2kByte of data in bidirectional way between CM7 and CM4.

Best regards,

Jochen

[JR1]

Where do I find the places in the code for the data array (memory) which is exchanged?

Is the same data array used for both exchanged data between the 2 cores?

[JR1]

Is there any simpler solution available for the shared mermory access? We just want to exchange 2KByte of data between the 2 cores.

[SofLit · Accepted solution]

See this thread: https://community.st.com/t5/stm32cubeide-mcus/easiest-way-to-share-data-between-cores-in-stm32h745/td-p/576140

Or just create a shared memory region common to the two cores on each Core's linker. But you need to ensure at least two things:

- Synchronization of read and write operation between the two cores using HSEM to ensure the consistency of the data.

- Either to manage the data coherency from CM7 side when Cache is enabled or declare that region as Strongly-Ordered or Device (non cacheable) using MPU.