Hello!
I'm new to DMA concept, and need some clarification on several DMA questions (STM32h7).
Q1. From RM0433: "To ensure data coherence, each group of transfers that form a burst are indivisible: AHB transfers are locked and the arbiter of the AHB bus matrix does not degrant the DMA master during the sequence of the burst transfer.
When the AHB peripheral port is configured for single transfers, each DMA request
generates a data transfer of a byte, half-word or word depending on the PSIZE[1:0] bits
in the DMA_SxCR register
• When the AHB peripheral port is configured for burst transfers, each DMA request
generates 4,8 or 16 beats of byte, half word or word transfers depending on the
PBURST[1:0] and PSIZE[1:0] bits in the DMA_SxCR register."
Do I understand correctly, that each DMA transfer length is defined by burst size, not by the the DMA counter?
Q2. If yes on Q1: Let's say I have several DMA peripheral-to-memory requests of the same priority:
USART1_RX - DMA1 Stream 0,
I2C1_RX - DMA1 Stream 1,
I2C2_RX - DMA1 Stream 2.
And I call these functions one after another:
HAL_UART_Receive_DMA(&huart1, UARTBuffer, 65534);
HAL_I2C_Master_Receive_DMA(&hi2c1, someI2C1Addr, I2C1Buffer1, 2);
HAL_I2C_Master_Receive_DMA(&hi2c2, someI2C2Addr, I2C2Buffer2, 20);
Is it right, that these DMA transfers will happen in "parallel"? Something like one (burst size) byte (half-word/word) from USART to memory, then one (burst size) byte (half-word/word) from I2C1 to memory, then one (burst size) byte (half-word/word) from I2C2 to memory. In other words, the stream with higher number won't have to wait for stream with lower number two reach NDTR=0.
