Setting the F407 FSMC WaitSignalPolarity default value

[Toneski]

Hi All,

I have a 407 connected to an FPGA using the FSMC interface.

When I compile my device configuration from ST Cube, the WaitSignalPolarity value in the MX_FSMC_Init routine is always set to: FSMC_WAIT_SIGNAL_POLARITY_LOW. On my system I need this setting to be FSMC_WAIT_SIGNAL_POLARITY_HIGH, but cannot find a way of setting this value through CubeMX.

Has anyone else found this issue or know how to fix it? Its getting a real pain having to manually update the source code before recompiling.

Kind Regards,

Tony

[Toneski]

Further info - I reconfigure the FSMC_BTR1 reg soon after the FSMC is setup. Do you think I should re-configure the Wait signal polarity here too?

// Correct configuration for FSMC BTR1 register.. (Appologies for the incorrect tabulation - your website screws it all up...

FSMC_BTR1 = (0 << 24) | // DATLAT

(5 << 20) | // CLKDIV - 1 doesn't work on the prototype, 5 defo works, but is slow - need to PCB this

// Gives 168Mhz/(5+1) for io clock :- 28Mhz, so 4 clocks for 16 bit word

// 5 clocks for 32 bit!!

// 7 MegAccesses for 16 bit = 14MB/s, 8.4MegAccesses for 32 bit = 22.4MB/s

(0 << 16) | // BUSTURN

(2 << 8 ) | // DATAST - No care for synchronous accesses

(15 << 4 ) | // ADDHLD - No care for synchronous

(15 << 0 ); // ADDSET - No care for PSRAM accesses

Regards,

Toneski

[FBL]

An internal ticket 167494 has been submitted to update the SVD file to include all BCR bit fields in STM32F4 SVD file and update FMC BCR register.

[Toneski]

Hi @FBL,

Thats great news. Is there anyway that I can access the internal ticket, so that I may watch its progress?

Also, do you know when this might be fixed? The next release maybe?

Thanks for all your help.

Regards,

Toneski