SDIO Hardware Flow Control

orders-st · ‎2013-12-16

Posted on December 17, 2013 at 05:03

Greetings all, I've been playing around with SDIO on an STM32F4 -Discovery card with the Embest Baseboard on it. My goal is to get it to work in polling mode, flow control mode, interrupt mode, and dma mode. This is for a book I am writing.

Generally the various bits of documentation can be puzzled out. But the flow control stuff is a bit of a mystery.

So I started with a polled version of my code, this does all the various commands and spin loops on the status register. And it works fine. So I wanted to demonstrate it doing ''flow control''. If I send a read command, and then delay pulling stuff out the FIFO, it fills up as expected but it doesn't stop filling. It just fills up, the clock keeps running, and CRC error comes on.

So I begin to wonder if I need things set in the DCTRL to make this work. I tried RWSTART, RWSTOP, and RWMOD (my setup is running a 4 bit bus so it needs to use SDIO CLK to stop things). None of them seemed to have any effect. (I still get essentially a RXFIFO overrun and CRC errors). So are there any additional docs on this feature of the SDIO peripheral?

--Chuck

#sdio-programming-flowcontrol

ivan23 · ‎2013-12-26

Posted on December 27, 2013 at 08:06

Hi Chuck,

I am currently working on a different MCU model, but there seems to be a global manufacturing or design error in SDIO HW flow control across most of the STM32F line- see

Errata sheet for silicon limitations of your specific STM32F407 MCU

http://www.st.com/web/en/resource/technical/document/errata_sheet/DM00037591.pdf

''

DocID022183 Rev 5 27/37

STM32F40x and STM32F41x STM32F40x and STM32F41x silicon limitations

36

2.9 SDIO peripheral limitations

2.9.1 SDIO HW flow control

Description

When enabling the HW flow control by setting

bit 14 of the SDIO_CLKCR register to ‘1’,

glitches can occur on the SDIOCLK output clo

ck resulting in wrong data to be written into

the SD/MMC card or into the SDIO device.

As a consequence, a CRC error will be reported

to the SD/SDIO MMC host interface (DCRCFAIL

bit set to ‘1’ in SDIO_STA register).

Workaround

None.

Note: Do not use the HW flow control. Overrun errors (Rx mode) and FIFO underrun (Tx mode)

should be managed by the application software

''

Steve Melnikoff · ‎2019-03-25

This isn't in the errata for the STM32L452xx series. Does it apply anyway?