Scheduling timers for motor control

[sb_st]

Hi!

I'm struggling to wrap my head around timers - I am trying to schedule some ADC reads of a current sense amplifier in a motor control setup.

I have three center-aligned PWM waveforms being generated by Timer1, which successfully commutate a BLDC motor. That's great. 

I would now like to schedule an ADC read once per PWM period. A simple first try at this would involve a single read right in the center of the PWM waveform. A slightly swankier version would be to calculate the largest duty cycle of my three PWM phases, and schedule my ADC read just after this point (but, again, just once per PWM period). 

I have experimented with configuring Timer1's TRGO to "Update Event", and scheduling my injected ADC read to be "Timer 1 Trigger Out Event". This, however, schedules the read at the beginning of the PWM period, rather than in the center of it. 

I'm also experimenting with setting up a slave timer - the idea being to trigger this secondary timer based on the above Timer1 TRGO trigger, and then being able to calculate a delay to either the center of the PWM waveform (Timer1 ARR) or after my largest PWM duty cycle (max(channel1, channel2, channel2) + offset). 

But this is where I'm getting confused - I can't quite wrap my head around how a slave timer behaves - I see One Pulse Mode, and each slave timer has its own PSC and ARR. There's a 'mode' parameter with options like "toggle on match", and a "Pulse" parameter which I think I understand to be the Capture Compare value for a given channel of the slave timer. I keep trying to modify these settings and scope the result on an oscilloscope, but I'm still having trouble building an intuitive understanding of what these parameters all mean. 

Would anyone be able to offer advice?

Thank you!

[Duc]

Hi @sb_st ,

Have you tried using "Output Compare No Output"?

In my setup, I’m working with the Nucleo-F446RE. I'm using Timer1 (Channels 1, 2, and 3) to generate PWM signals. For Channel 4, I’ve configured it as "Output Compare No Output" with the mode set to toggle on match. This triggers when the timer's counter reaches the halfway point of the cycle. For my three ADC channels, I've set them to be triggered externally by the "Timer1 Capture Compare 4 event", and I've configured the external trigger to detect both rising and falling edges.

[sb_st]

Thank you! Can I ask - is your setup for inline current sensing perhaps?

I ask because my setup is for low-side sensing. As I understand it, your setup yields reads at the beginning and 'center' of the PWM cycle, which would be fine for inline sensing, but wouldn't work for low-side as I need to constrain my reads to only when the low-side FETs are on. I think triggering the ADCs on only either the rising or falling edge (depending on which falls in the center of the waveform) would get me close. 

However, as I've been experimenting with this, it seems that I'm unable to trigger at ARR-1, which would be the 'center point' of the PWM - instead, I seem to only be able to see my ADC callback firing when I set my trigger to ARR - 2 or more. This, as I understand it, would yield two reads in rapid succession, is that right?

Can I ask a followup about the ADC reads themselves? I think I understand that I would ideally like to read U, V, and W voltages simultaneously. To do this, I have ADC1, ADC2, and ADC3 configured in "Triple Combined Regular Simultaneous + Injected Simultaneous mode" (what a mouthful!). I would also like to read VREFINT periodically, as well as a bias voltage being applied to my sense amplifiers. I am struggling to understand how to choreograph these reads. May I ask how you have this set up?

Thank you so much!

[Duc]

No @sb_st ,my setup triggers the ADCs at the midpoint of the PWM cycle. Whether you use the low or high side is up to you — it’s fully configurable.

For reading the U, V, and W phases, I’m using Independent Mode with Injected Conversion Mode. Whenever the timer counter matches the compare value I’ve set, it triggers the ADC. Since I know the PWM period, I can calculate its midpoint and set the corresponding compare value so that the ADC samples right at the center of the PWM period.

As for VREFINT, how frequently you sample it depends on your application. You’ll need to configure the timer and ADC accordingly.

To achieve your goal more effectively, I recommend getting familiar with how timers work on the STM platform first.