> I've just been dropped into the middle of a project ...
Congratulations! Ain't it great?
Guidelines for data cache management to avoid nasty surprises:
- Align a buffer that's shared with an "active accessor" (e.g., DMA) to an address boundary equivalent to the data cache line length.
- Set the overall length of a buffer that's shared with an active accessor to be an integral number of cache lines. Note that the entire length of these shared buffers may or may not be used by the active accessor but the "integral number of cache lines" length becomes very important when you ...
- Flush (terminology in use for decades before the silly, made-up "clean") the data cache before allowing/enabling an active accessor's read of the buffer. The base address of the data cache flush operation is the cache-line-length-aligned address described above. The length of the data cache flush operation is the overall length of the buffer (i.e., an integral number of cache lines) described above. Note that the overall length of the buffer passed to the flush many not necessarily be the length of the memory area the active accessor sees but it must be an integral number of cache lines.
- Invalidate the data cache after an active accessor's writing to a (cached) buffer is complete. The base address of the data cache invalidate operation is the cache-line-length-aligned address described above. The length of the data cache invalidate operation is the overall length of the buffer (i.e., an integral number of cache lines) described above.
The reason for the (sometimes awkward) buffer alignment and length criteria are to prevent potential corruption of memory adjacent to the buffer due to the flush and invalidate operating on whole cache lines.
