The immediately obvious main problem in your layout is the insufficient GND of the crystals, which, as mentioned, has a particular effect on the LSE. If you take a look at section 7.2 in the aforementioned AN2867, e.g. fig. 14, you will notice that:
- each crystal has its own GND area on the underlying layer, which is also separated from the other GND (visible with a white line)
- each of these GND areas is connected to a GND ring on the component side with several vias, which creates something like a GND trough around and under the crystal
- these GND areas are routed separately to the next possible GND pin of the STM32
I strongly recommend to adjust this in your layout.
You haven't shown the other layers under the crystal, but if there are tracks with signal edges, the problem is exacerbated.
Regards
/Peter
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