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RTC oscillator STM32F407

Michael99
Associate II

Hello,
I am using a CC4V-T1A-32.768KHZ-12.5PF-20PPM-TA-QC crystal with 22pF caps on a STM32F407ZGT6.problem with some devices the crystal does not oscillate.could the crystal or the capacitors be wrongly designed?
What can we change?
Thanks for your help

8 REPLIES 8
Peter BENSCH
ST Employee

Welcome @Michael99, to the community!

Problems with the very sensitive LSE have often been discussed here on the community. They occur if you do not follow the recommendations of AN2867 closely enough, where sections 7.1 and 7.2 in particular provide detailed instructions.

What does your layout around the LSE Crystal and the STM32 look like?

Regards
/Peter

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Michael99
Associate II

Hello Peter,
Thanks for the quick reply.
Attached is a part of the board with the LSE Oscillator.
We have tested leaving out the two capacitors on the quartz, result: the quartz oscillates.
We did the stability calculations for the AN2867 and the result was ok.
Is it better to use a crystal with a smaller load capacitance, perhaps 6pF?

Greetings
Michael

 

LSE Oscillator.png

Peter BENSCH
ST Employee

The immediately obvious main problem in your layout is the insufficient GND of the crystals, which, as mentioned, has a particular effect on the LSE. If you take a look at section 7.2 in the aforementioned AN2867, e.g. fig. 14, you will notice that:

  • each crystal has its own GND area on the underlying layer, which is also separated from the other GND (visible with a white line)
  • each of these GND areas is connected to a GND ring on the component side with several vias, which creates something like a GND trough around and under the crystal
  • these GND areas are routed separately to the next possible GND pin of the STM32

I strongly recommend to adjust this in your layout.

You haven't shown the other layers under the crystal, but if there are tracks with signal edges, the problem is exacerbated.

Regards
/Peter

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We only have one small problem.
The layout is in series production. All approvals have been completed.
Is there any other possibility than changing the layout?

BarryWhit
Lead II

@Michael99 , according to design procedure formula on page 13 of AN2867, 22pF is probably too large a value for a crystal that specified CL=12.5pF. You suggested perhaps using 6pF - this tells me that your guessing at the value instead of calculating it. If you want to do it that way, test very possible value between 6pF-22pF and establish a range that works, then pick a value. Or:

 

- Do the calculation from page 13 and that value and values around it. The parasitic capacitance of the crystal to the surrounding board is generally unknown but usually on the order of a few pF, so some trial-and-error is required to dial in a value. 

- Once you found a capacitance value (even better, a range of values), repeat the process for as many boards as you can justify, to make sure they ALL work - there's no point in making one board work and making others stop.

- If this fixes the issue, you've probably identified the cause.

 

Note that this only gives evidence of proper functioning under "typical" conditions, not "worst-case" conditions. Remember that capacitance varies with temperature (depends on dielectric), age, is specified only up to some tolerance, and other factors. So you should do at least at least wave a hair-dryer over it and see if it still starts up. Unless you intend to deploy your product in the Nordic countries, in which case you should place it on a block of frozen Lutefisk instead. And if you're developing a commercial product that has Max operating condition specified, you obviously have to closely test for those.

 

Peter correctly point out that PCB layout is important for proper crystal functioning, and that the appnote was written specifically to help you do that (and I know he is secretly heart-broken since everyone on the forum who reports oscillator issues always seems to have ignored the appnote's layout guidelines completely). But it's also important to note that, practically speaking, many designs violate some of the guideline and still work under typical conditions (and beyond). It's just more risky to do so. So I wouldn't immediately suspect the layout as being the cause unless you've done something completely horrible (though the layout may be the issue after all). You do ultimately want good layout because it reduces risk and mitigates *potential* issues, not because following every guideline is absolutely necessary for your product to function. 

 

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STOne-32
ST Employee

Dear @Michael99 ,

a Crystal with CL = 12.5pF  will not work on STM32F407 MCU , please select from your crystal manufacturer a CL=6pF and then to calculate the gain margin as detailed above by @Peter BENSCH  and @BarryWhit .

the most critical parameter for a crystal is ESR Max and should be  small enough to have a gain margin of 3 at least . 

Micro crystal is among our partners and can provide you that reference keeping same footprint of your final PCB 

IMG_9233.jpeg

IMG_9234.jpeg

then CL1 and CL2 should in range of (2 * CL ) - 2 *3pF as my rough estimation of your design - so if CL=6pF , they should be in range of 6pF and if CL=7pF , they should about 8pF.

 

the main drawback of such crystal with low CL is the pullability factor and 12,5pF as the best in a harsh environment. But excellent for low power and battery operation 

Hope it helps you 

STOne-32

BarryWhit
Lead II

AN2867 is not a shining example of good technical writing, to say the least.

 

I think @STOne-32  is referring to section 3.4 of the appnote,  "oscillator transconductance", which gives a formula and tests to check for suitability of a crystal. 

 

Your crystal with a CL=12.5pF spec fails those tests, but the same crystal with CL=6pF qualifies.

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- Please post an update with details once you've solved your issue. Your experience may help others.

Hi
As you suggested, I have installed a quartz crystal with a capacitance of 6 pF and load capacitances of 6 pF. The result is that the crystal does not oscillate.
Do you have any other ideas?