RMII or MII?

[ezrab]

Posted on January 20, 2011 at 08:47

RMII or MII?

[ezrab]

Posted on May 17, 2011 at 14:22 of course it has to be precise  that is why there is a special line called ETH_RMII_REF_CLK int the STM32 to make sure it works. right?

[js23]

Posted on May 17, 2011 at 14:22

Yep, ETH_RMII_REF_CLK is the input for the 50Mhz clock for the STM32 MAC. In normal RMII mode, the same clock has to be applied on PHY REF_CLK input.

When using the ''25MHz Mode'' (or ''REF_CLK out mode'', or whatever you call it) the PHY can generate the 50Mhz clock which has to be connected to STM32 ETH_RMII_REF_CLK, of course. Until now I only used the 50MHz generated by the STM32 PLL3. This was proven to be working and has the advantage that only 1 crystal is needed for the whole system. But whatever you do - timing and especially clock jitter has to be within limits.

[ezrab]

Posted on May 17, 2011 at 14:22 how can i output the PLL clock of 50MHz and work in the STM32 in higher freq? basicly what i want to do is this to connect one or two 25Mhz cristal. stm32 work with RMII and with internal freq of stm32  in 120MHz. is it possiable? thanks.

[js23]

Posted on May 17, 2011 at 14:22

Yes, I used MCO output from PLL3. One 25MHz crystal is sufficient to generate 50Mhz for RMII and 72Mhz for CPU. But this is for F107. Cannot tell you much about the F207 - only that I think it should be possible, too...

[ezrab]

Posted on May 17, 2011 at 14:22 OK thats one way how about this way i will connect the 25MHz cristal to the stm32 and  to the PHY and the REF_CLK OUTPUT of the PHY will be connected to the ETH_RMII_REF_CLK. basicly my question is can the STM32 work with 25MHz cristal and 50MHz input in the ETH_RMII_REF_CLK? is the MAC clock seperated from the system clock?

[Tesla DeLorean]

Posted on May 17, 2011 at 14:22

The F2 supports clock inputs or xtals between 4 and 26 MHz.

So you could use a 25 MHz TCXO, and use whatever combination of PLL dividers/multipliers to get to 120 MHz or a rate you need. I haven't looked at the F2 settings, but other than the key frequencies you require, the actual CPU and BUS speeds can typically be quite flexible, and can usually be tweaked to achieve your bandwidth/power goals.

[ezrab]

Posted on May 17, 2011 at 14:22 yes i know but is the MAC clock seperated? which mean that the system clock is something else from the MAC clock that its sorce is ETH_RMII_REF_CLK? thanks.

[js23]

Posted on May 17, 2011 at 14:22

Yes, system clock is independent from REF_CLK. So using the PHY ''25 MHz Mode'' should not be a problem. But you are doing many new things (new uC, new PHY, new mode..) so according to my (and Murphys) experience, you will have problems... ;-)

Anyway, I would really recommend to stay close to some existing design (are F2x demo boards already available?). If the F2x would be sampling to the not-so-important-customers like me, I would already have it placed on my board and could tell you more...