RAMECC with Dcache

[KevinG]

I am working on a Nucleo-H753ZI board looking at RAMECC.

My code is based on the example at
https://github.com/STMicroelectronics/STM32CubeH7/tree/master/Projects/NUCLEO-H745ZI-Q/Examples/RAMECC/RAMECC_ErrorCount

I am using debug to watch the status of the RAMECC registers at HAL_RAMECC_IRQHandler in stm32h7xx_hal_ramecc.c using Memory Browser.

I get sensible numbers, such as:

0x52009024  RAMECC_M1SR     00000001
0x52009028  RAMECC_M1FAR    00000174
0x5200902C  RAMECC_M1FDRL  BB6A6546
0x52009030  RAMECC_M1FDRH  0488EBAA
0x52009034  RAMECC_M1FECR  00000031

However, if I turn on Dcache using SCB_EnableDCache(); in main.c I mostly get 0x03 in RAMECC_M1SR,
which would suggest both a single and double error.

Does it make sense to have a status of both single and double error if Dcache is turned on?
If yes what sort of error do I treat it as in terms of correcting it (do I assume it is a double error and therefore not correctable)?
If not is there something I can do so that only 0x01 or 0x02 appears in RAMECC_M1SR with Dcache enabled?

[PaulMadle]

Hey Kevin,

We are also finding similar behaviour, if the dcache is enabled, we enable the RAMECC and then trigger some errors (by reading uninitialised RAM), we see the same thing... 

RAMECC_M1SR contains 0x3 not only in the memory monitor for the area where we are performing the test but also on the other monitors associated with the domain in question??

Is this a problem with the chip? Do the RAMECC registers start behaving strangely when you enable dcache? How can we work around this?

[CharlieGallie]

I could do with the answer for this too.

It seems there's some correlation described in the STM32H753 Errata Sheet, section 2.1.1.

Maybe this is the cause of the issue? Other than that, I'm having a hard time understand why this happens.