question about DMA

[helixwmonkey]

Posted on May 04, 2014 at 16:44

I have an ISR, in which a DMA transfer will take place when the ISR is running. Although DMA transfer does not occupy CPU's running time, but occupies the Data bus. So will the DMA's existence lengthen the ISR's execution time? (In the ISR, some variables are read and write, and some calculations are carried out.) What kind of instruction's execution time will be influenced by DMA transfer, for example LDR & STR?

Thanks.

[waclawek.jan]

Posted on May 04, 2014 at 17:47

> What kind of instruction's execution time will be influenced by DMA transfer, for example LDR & STR?

Although I know of no good description of how the bus matrix arbitration in STM32 works, my benchmarking experiments on STM32F4 showed that LDR will definitively see a one cycle penalty after the DMA accessed the same slave bus. STR in CM3/CM4 goes through a buffer so it may go without a penalty; AFAIK CM0 is different but I have no experience with those. The picture may/will get more complex with multiple successive load/store, unaligned accesses, code being fetched through the system bus, etc. JW

[Tesla DeLorean]

Posted on May 04, 2014 at 18:22

Yes, don't want to be dwelling in the IRQ Handler for long periods. You might want to light off a DMA transaction, and then catch the completion at DMA TC