QuadSPI Single SPI mode IO2 state

[frackers]

In Single SPI mode, the unused qspi pins are held as follows:

 IO2 is in output mode and forced to ‘0’ (to deactivate the “write protect�? function)

 IO3 is in output mode and forced to ‘1’ (to deactivate the “hold�? function)

Problem is, all the flash chips I've looked at (W25Q128, N25Q512 etc) the Write Protect pin is active low so by forcing IO2 low, the write protect is activated. This means that I can't write or erase the chip unless I get it into full quad mode.

Am I missing something here ?

[rowant]

Hi frackers,

This is normal and just fine, the write protect pin simply protects writes to the memory, not the registers of the flash chip.

When you enable QPI by writing to the status register (don't forget to write enable first), IO2 & 3 will then change to the correct mode.

If you're using the HAL, configuring the QSPI_CommandTypeDef with the correct mode's (QSPI_INSTRUCTION_1_LINE, QSPI_ADDRESS_1_LINE, QSPI_DATA_1_LINE etc), the pins will be configured correctly automatically for that mode.

Example to setup to write in Single SPI mode:

QSPI_CommandTypeDef cmd = {
			.Instruction = QSPIF_PROG,
			.Address = writeAddr,
			.InstructionMode = QSPI_INSTRUCTION_1_LINE,
			.AddressMode = QSPI_ADDRESS_1_LINE,
			.AddressSize = QSPI_ADDRESS_24_BITS,
			.DataMode = QSPI_DATA_1_LINE,
			.NbData = lengthToWrite,
	};
// Send the command (this sends the instruction and address value)
HAL_QSPI_Command(&hqspi, &cmd, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
 
// Write the data (this transmits the data of length cmd.NbData)
HAL_QSPI_Transmit(&hqspi, data, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);

[Andreas Bolsch]

Just reconfigure the pins connected to IO2 and/or IO3 to GPIO outputs momentarily, then you can assign any state to them. No need to disable the QSPI interface for that. One write to the MODER register, that's it.

BTW: Check the flash's data sheet carefully. The WP input does not (at least on some chips) write protect the memory array by itself, but protects the block write protection flags from beeing changed. So, if no block protection is engaged (usually the default when shipped), the memory array is writeable regardless of the level on the WP pin.

E. g. W25Q128FV: "The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low."

[frackers]

I'm using a W25Q128FV and I was concerned that preventing the Status Register from being written stops the Write Enable bit being set and hence no write or erase.

Hence my query which you seem to have confirmed, i.e. STM have got the default signalling in Single SPI mode for IO2 the wrong way up!

[Andreas Bolsch]

No, I think it's in fact the most sensible default they implemented: In default setup of the flash chip (upon shipping) the memory array is writable *REGARDLESS* of the state of WP pin.

However, if a portion is to be protected, one would change WP to '1' temporarily, engange the proper protection bits in the flash's register, then release IO2 pin from GPIO control, so that it reverts to the default '0'.

Now the unprotected blocks can still be modified without touching IO2 again (note that the Write Enable flag is not affected by WP, it's a volatile flag only), whereas the protected ones can no longer be modified accidentally as the protection can't be easily undone again.