PWM input falling edge capture behavior

[Eetu Nevalainen]

Hi,

I'm following RM0390 reference manual's PWM input mode example for calculating frequency and duty cycle for incoming PWM signal. Basically I'm using TIM1's CC1 for capturing rising edges and CC2 for capturing falling edges. The question is that is it normal for CC2 to be triggered twice in a period? It seems that in my case CC2 is also sensitive for rising edges. Is that due to timer reset?

If the behavior described above is normal, do I just discard the CC2 value when CC1 gets triggered? Also if I want to use input capture prescaling do I configure IC2PSC to be twice as many events as IC1PSC?

Here's my TIM1 register just after CC1 and CC2 have been enabled.

[waclawek.jan · Accepted solution]

You've set both CC2P and CC2NP in CCER, that's both edges sensitivity.

JW

[Eetu Nevalainen]

Thanks! Looks like disabling CC2NP bit solves my problem. I re-visited RM0390's PWM input mode example and it states that both CC2P and CC2NP should be enabled. Maybe I have misunderstood something.

[waclawek.jan]

Eetu,

Humm, that's a bug in the manual. Thanks for letting us know.

I randomly selected RM0090 rev.18 and it's incorrect in 2 out of the 3 incarnations of the PWM input mode subchapter (it's correct in the TIM2-TIM5 chapter). I guess it will be similar for RM0390.

@Imen DAHMEN​  this probably goes across many STM32 TIM chapters, can somebody please have a look at it?

Thanks,

JW

#sloppy_manual_revisioning

[Vincent Onde]

​Hi @Community member​ ,

I'll take care of this. It will be changed in the source file and will be visible when new user manuals will be published.

Best regards,

Vincent

[waclawek.jan]

Thanks, Vincent.

Jan

@Vincent Onde​