Pulse edge detection level of STM32 Timer input capture

[BOh.1]

I'm using STM32F407 and I want to capture a pulse of following detail:

Frequency: 100~1000 Hz

LOW voltage: 0.7v

HIGH voltage: 1.5v

and I'm wondering that whether STM32 input capture can be triggered on such 0.7~0.8V height pulse, or not.

If not, what is the input capture edge detection trigger condition?

Thank you in advance for your help.

[waclawek.jan]

As in the ChatGPT-generated spam @LBett.1​  above (which the Moderators will probably delete soon) says, quite correctly, you have to look into the Datasheet to check the inputs' decision levels. As you can see, it depends on the power supply voltage.

 

There are two values given, which is confusing, but the reason is explained in footnotes: (1) is the design value, (2) is value tested in production.

Assuming 3.0V VDD, for falling edge VIL applies, i.e. the signal must go below 1.0V to be seen as low. For rising edge VIH applies, i.e. signal must go above 2.1V to be seen as high. Even the less stringent design value requires at least 1.65V to detect reliably high. So, if VDD is 3.0V, your signal won't be reliably detected.

You might be able to find a particular VDD where both levels would be satisfied; however, generally, it's a better idea to condition the input signal e.g. using a comparator or an appropriate digital input buffer IC - as the chatbot suggested it, too.

JW