Problem with IWDG and WWDG timeout

[Damien-HACKETT]

Hello ST Community and Support Team,

I try to play with Independant Watchdog and Window Watchdog on a Nucleo U575ZI eval board.

I was able to configure counters, window and even EWI interrupt perfectly thanks to STM32 HAL library watchdog related functions and see a reset when timeout is too low and no reset when the refeeding is done on time.

==> I have now problems setting the correct value to have the expected timeout of around 2 seconds I want.

1) On WWDG, the prescaler schematic is pretty clear and with ST example code with counter = 0x7F and prescaler 64, we expect to have around  209,71ms of timeout with the following formulas :

WWDG Counter Clock = PCLK1 / (4096 * Prescaler) 

WWDG Counter Time (ms) = 1000 / WWDG counter clock

WDG Timeout (ms) = Counter settings * Counter Time

So theorically, with PCLK1 = 160MHz, we can reach only around 419ms maximum when using PRESCALER 128 and Counter 0x7f right ?

When doing some experiment on my board with this last settings, I have only decreased of around 8 counter ticks (so not generating a reset as we reach 0x77) in 500ms in Debug mode, can you explain how ? My project was generated with CubeMX so PCLK was set to 160MHz...

2) On IWDG, all work correctly and seems to be good to reach the 2 seconds target, it is just the using the following formula I cannot get the exact same result as what is shown in ST example test (Counter = 1561 (in decimal), PRESCALER 16, by calculus : 780 ms whereas ST example claims for 736ms....)

IWDG Clock= LSI / Prescaler

IWDG Counter Time (ms) = 1000 / IWDG clock

IWDG Timeout (ms) = Counter * Counter Time

LSI clock is 24KHz as I not enable the /128 Prescaler before IWDG.

=> Can you point me where I do wrong in my formula ?

Nice regards,

[TDK · Accepted solution]

The datasheet shows calculations for min/max timeouts under various conditions.

Note that there's a typo here at least. The Prescaler "46" should be "64".

> LSI clock is 24KHz as I not enable the /128 Prescaler before IWDG.

Note that LSI is 32 kHz, not 24 kHz.

Reference manual suggests the prescaler can be 1024. I'd trust the RM over the DS.

> what is shown in ST example test

Your math seems fine. What test are you referring to? Link it.

[Damien-HACKETT]

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@TDK wrote:

The datasheet shows calculations for min/max timeouts under various conditions.

Note that there's a typo here at least. The Prescaler "46" should be "64".

==> Ok so I have the same value than the datasheet so my IWDG should be well configured. That solve problem 2.

> LSI clock is 24KHz as I not enable the /128 Prescaler before IWDG.

Note that LSI is 32 kHz, not 24 kHz.

==> Yes sorry 32KHz.

Reference manual suggests the prescaler can be 1024. I'd trust the RM over the DS.

==> This is the prescaler of IWDG that can go up to 1024, the one for WWDG is maximum to 128 (but we can try to reduce PCLK1 but it is not what I want).

I will probably check if there is an issue on the PCLK value making WWDG count down very slowy...

> what is shown in ST example test

Your math seems fine. What test are you referring to? Link it.

Here the example code as use as reference and that clairly said that it set iwdg counting for 762ms :

https://github.com/STMicroelectronics/STM32CubeU5/blob/8581ab856c60da93b2c4e649449c1e8242914a37/Projects/NUCLEO-U575ZI-Q/Examples/IWDG/IWDG_WindowMode/Src/main.c#L39

Maybe the value was updated but not the comment. Classic :)

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[TDK]

Generally, when a new chip series comes out (e.g. the U5), the examples, documentation and code quality lag behind a bit. Likely that's what is happening here.

Agreed, seems like the comment is just wrong. Probably if you dig into similar examples on other chips you would find one of them where the math in the comment is correct and it just wasn't updated for this example.