H7 DMA & BDMA: Double Buffer Mode (DBM) timing, CT vs TC interrupt

[LCE]

Heyho,

I had probably some race condition, just want to make sure:

the buffer switching in DMA's Double Buffer Mode (DBM) (both for DMA and BDMA) occurs immediately with the Transfer Complete (TC) interrupt?

So when the DMA's TC ISR is entered (which takes a few CPU cycles), the buffer has already been switched and the CT (Current Transfer, showing if the buffer in M0AR or M1AR is active) has already been switched?

STM32H733

[LCE]

@STea or @Peter BENSCH maybe?

[waclawek.jan]

Good question especially in light of NDTR not being a good indicator of transfer completeness.

So, the question is, what is the exact timing of TC and CT with regard to the peripheral and memory side of the last transfer before NDTR reload?

(BDMA/single-port DMA is a different case and I'd be surprised if that would be problematic; I am surprised it does have the DB mode which must be unique in 'H73x or is it present in other single-port DMAs too?)

JW

[STea · Accepted solution]

Hello @LCE ,

the short answer for your question: 
"The buffer switching in DMA's Double Buffer Mode (DBM) (both for DMA and BDMA) occurs immediately with the Transfer Complete (TC) interrupt?" 
is yes. In fact, in DMA's Double Buffer Mode (DBM), the buffer switching occurs immediately upon the Transfer Complete (TC) interrupt. When the TC interrupt is triggered, the buffer has already been switched, and the Current Transfer (CT) bit, which indicates whether the buffer in M0AR or M1AR is active, has already been updated.

Regards