Problem in switching the SYSCLK to MSI in STM32CubeHALv1.7.0

[Wassim Ben Chikha]

Posted on October 02, 2017 at 10:39

Hi,

I

n

the HAL_RCC_DeInit function,

switching the SYSCLK to MSI

only

uses

this function

CLEAR_BIT(RCC->CFGR, RCC_CFG_SW)

. But, to select MSI as system clock source, I think that it is required to use

after that

th

e following

instruction

SET_BIT(RCC->CFGR, RCC_CFGR_SW_MSI). Please, can you verify if there are some problems in the function HAL_RCC_DeInit?

Many thanks for your time and look forward for your response.

Best regards,

Wassim Ben Chikha

[Imen.D]

Posted on October 02, 2017 at 18:17

Hello,

Could you please precise in which STM32Cube HAL library you have found this issue?  So, we can verify it.

If you are using an old version

of Cube firmware package

 try to use the latest. Then, please let us know if the issue still exist with the last version.

Best Regards

Imen

[Tesla DeLorean]

Posted on October 02, 2017 at 19:13

Using STM32L152RE

[Imen.D]

Posted on October 03, 2017 at 10:43

Hi,

Thank you for sharing the details. I will check your reported issue, then raise it internally if confirmed.

I will keep you informed about the taken actions or explanation if needed.

Kind Regards,

Imen.

[Wassim Ben Chikha]

Posted on October 03, 2017 at 09:28

I use the STM32L152RE device with STM32CubeHALv1.7.0. Note that the function is implemented in stm32l1xx_hal_rcc.c (version V1.3.0 developed in 21-April-2017). In the following, you can see the function.

----------

void

HAL_RCC_DeInit

(

void

)

{

/* Set MSION bit */

SET_BIT(RCC->

CR

, RCC_CR_MSION);

/* Switch SYSCLK to MSI*/

CLEAR_BIT

(RCC->

CFGR

, RCC_CFGR_SW);

/* Reset HSION, HSEON, CSSON, HSEBYP & PLLON bits */

CLEAR_BIT

(RCC->

CR

, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_HSEBYP);

/* Reset CFGR register

CLEAR_REG(RCC->

CFGR

);

/* Set MSIClockRange & MSITRIM[4:0] bits to the reset value */

MODIFY_REG(RCC->

ICSCR

, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), ((0U << RCC_ICSCR_MSITRIM_BITNUMBER) | RCC_ICSCR_MSIRANGE_5));

/* Set HSITRIM bits to the reset value */

MODIFY_REG(RCC->

ICSCR

, RCC_ICSCR_HSITRIM, (0x10U << POSITION_VAL(RCC_ICSCR_HSITRIM)));

/* Disable all interrupts */

CLEAR_REG(RCC->

CIR

);

/* Update the SystemCoreClock global variable */

SystemCoreClock = MSI_VALUE;

}

---------

Note: The HAL_RCC_DeInit function does not execute. Indeed, the execution is stopped in the function of switching the SYSCLK to MSI.

Many thanks for your time and look forward for your response.

Kind regards,

Wassim Ben Chikha

[Yohann M.]

Posted on October 05, 2017 at 11:01

Hello,

The implementation is correct. To switch MSI to the system clock, value in the bit CFGR_SW should be equal to 0.

This is done with CLEAR_BIT macro.

A problem we may have in this function is that we don't wait for MSI RDY bit after switch on it.

----------

void

HAL_RCC_DeInit

(

void

)

{

/* Set MSION bit */

SET_BIT(RCC->

CR

, RCC_CR_MSION);

  /* Wait till MSI is ready */

while (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) {}/* Switch SYSCLK to MSI*/

CLEAR_BIT

(RCC->

CFGR

, RCC_CFGR_SW);

(...)

[Imen.D]

Hello,

This issue is fixed with the STM32CubeL1 FW V1.9.0 release.

Thanks

Imen