Practical DMA transfer speed from MEM to PER?

[IIvan.12]

Hello community,

I wrote program that use MEM to PER transfer, HALF WORD mode (16 bit). DMA transfers are clocked by TIM1. MCU is stm32f103c8t6 @ 72Mhz on "Blue Pill" board. As final result I got 16 bit sample values on PORTB at 360kHz speed. It seems too low . Theoretically I read that MCU can perform DMA transfers on about 40% of clock speed, which mean about 30MHz. What are DMA speed which you reached and where can be my mistake?

[waclawek.jan]

> Theoretically I read that MCU can perform DMA transfers on about 40% of clock speed,

Where did you read that?

Read AN2548.

JW

[IIvan.12]

Did you mean "Using the STM32F1x and STM32L1x DMA controller (AN2548)" - zip file with some example projects how to use DMA controller? If YES I not seen how it can help me:

1. Examples on my fast look shows data direction GPIO->SRAM, but I use reversed direction SRAM->GPIO.
2. The program which I wrote works - it configures TIM1, it configures DMA controller then all transfer runs over hardware. On this point I can only decrement values into TIM1 i.e. increment transfer speed and measure it and I reach 360kHz.

So my question remain ..... what is PRACTICAL transfer speed which someone really obtained using SRAM->GPIO DMA transfer.

May be the problem is that on "Blue Pill" probably is soldered counterfeit device or may be not?!

How examples from AN2548 can help me to understand REAL DMA transfer speeds?!

Ivan

[waclawek.jan · Accepted solution]

No, I mean the application note, https://www.st.com/resource/en/application_note/cd00160362-using-the-stm32f0-f1-f3-g0-lx-series-dma-controller-stmicroelectronics.pdf

It describes, how the DMA works, although unfortunately not in much detail.

Basically, it performs some arbitration (1-2 AHB clocks), reads on the source side (in your case SRAM, if there's no conflict on the bus with other busmaster e.g. processor, 1-2 AHB), then writes on the destination side (maybe 1-2 AHB clocks, then whatever sync happens in the AHB-APB bridge, then at least one APB clock - the 'F1 is the first STM32 and the only where GPIO are on APB). Very roughly, count 6-10 AHB clocks per transfer, i.e. say around 10M transfers per second. If you transfer successive ones and zeros, you'll see half the transfer rate as output frequency.

> May be the problem is that on "Blue Pill" probably is soldered counterfeit device or may be not?!

That, of course, is possible. Or, maybe these days, likely.

JW

[IIvan.12]

Many big thanks JW,

pointed by you application note is enough detailed and helped me to understand real situation. So as practical report:

1. I use DMA transfer for only one task and match situation as described into App Note "For the case where only one DMA channel is active, a new hardware back-to-back request can not be handled by the DMA before the completion of the previous one, adding one AHB clock cycle for the final idle phase of the DMA request-acknowledge handshake protocol. " - this mean 7 clocks per transfer (match in calculated by you 6-10 clks. range)
2. By point 1, if I set TIM1 Prescaler to 0 and Period to 7 I got maximal transfer speed which is - 10.28Mhz.
3. If I set TIM1 Period to 6 or lower I go into situation where: "Data lost without overrun flag – possible for example in case a GPIO port is configured as a parallel communication port" (quoted again from App note)
4. With every value greater than 7 output frequency is lowered.

Kind Regards

Ivan