a footnote(4) in STM32H7 reference manual RM0468 Table 56 regarding the maximum allowed frequency for ADC says
"With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even".
Does this recommendation apply to the actual DIVXx register bits value or the resulting actual divisor /(DIVXx + 1) ?
Or, in other words, is DIVR2[6:0]=0000010 (ie. /3) be regarded even (0000010) or odd (/3) and thus not well suited in this context? I assume the latter?
Thanks for clarification
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