About Kolja Waschk

Kolja Waschk · 2023-08-14

Hi,a footnote(4) in STM32H7 reference manual RM0468 Table 56 regarding the maximum allowed frequency for ADC says"With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even".Does this recommendation apply to the actual DIVXx regist...

Kolja Waschk · 2022-03-04

Hi,I experience strange behaviour with the just reworked H7 ethernet driver in STM32H725 with LwIP + FreeRTOS environment. A continuous transmission of UDP frames (bursts of 3..4 frames every ~ 50 ms) comes to halt after just a few successful loops. ...

Kolja Waschk · 2022-02-16

Hi,I'm currently setting up ADC1/2 of STM32H725IGx, using STM32CubeMX 6.3.0 with FW_H7_V1.9.0. They are configured to run at async ADC clock, which is about 126 MHz defined in CubeMX Clock Configuration, divided by 4 => 31,5 MHz.However, sampling and...

Kolja Waschk · 2021-06-30

Hi,on H723... I'm trying to configure a DMA on TIM5 CC3 event (DMA1 Stream 0 P2M) to capture the current NDTR value of another stream (DMA1 Stream 1 P2M) (to record where that DMA just put data from ADC into a ring buffer at the time of the CC3 event...

Kolja Waschk · 2018-01-09

Posted on January 09, 2018 at 18:32Hi,Using CubeMX, I configured SPI1 on a STM32F103T8Ux as full-duplex master mapped on PB3..PB5, with hardware NSS (on PA15) disabled (set to SPI_NSS_SOFT in spi.c).So, PA15 should be available for TIM2 CH1 PWM outp...

Kolja Waschk · 2022-03-05

Never mind.. the static "heth" structure in my system sometimes wasn't all zero at startup before low_level_init() (which doesn't zero its contents either). So the success of the initialization and everything after was dependent on some prior state (...

Kolja Waschk · 2022-03-04

The behaviour changes as I further add or remove debug code. Might as well be timing related, but I'm running out of ideas currently. Sometimes even with the read access the MAC stalls. I double-double checked the MPU settings and placement of descri...

Kolja Waschk · 2022-02-16

I currently have configured VOS1. Table 56 shows 160 Mhz limit with VOS1. How is this related to the limitation on Fadc that I experience? I get 126,5 MHz from PLL2P (which is below 160) and I'm not allowed to feed this divided only by 2 into f_adc_k...

Kolja Waschk · 2022-02-16

Ah! That dependency is new to me. After changing current setting (VOS1) to VOS0, smaller divisors and thus higher clocks can be chosen.Can you help me to locate the relevant documentation about the limitation on the Fadc or due to voltage scaling? Un...

Kolja Waschk · 2022-02-16

(sorry typo 15 Hz => 15 MHz)

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PLL clock division in STM32H7 for fadc_ker_ck

STM32H7 Ethernet transmission comes to halt, eventually related to TX queue underflow interrupt?

STM32H725 ADC1/2 run at half the configured speed?!

How to capture NDTR of ADC DMA on timer event

STM32F103XB: TIM2 CH1 on PA15 conflicts with SPI1 NSS

Re: STM32H7 Ethernet transmission comes to halt, eventually related to TX queue underflow interrupt?

Re: STM32H7 Ethernet transmission comes to halt, eventually related to TX queue underflow interrupt?

Re: STM32H725 ADC1/2 run at half the configured speed?!

Re: STM32H725 ADC1/2 run at half the configured speed?!

Re: STM32H725 ADC1/2 run at half the configured speed?!