cancel
Showing results for 
Search instead for 
Did you mean: 

OCTOSPI line idle level - Weird behaviour

Gabriel_Csefalvay
Associate II

Hi, Community,

I'm trying to understand the OCTOSPI peripheral on my STM32L4P5. I'm new to STM32, but old in embedded. Particularly, I need to know/affect the idle level of the data line of the OCTOSPI. I thought that the last transmitted bit would remain there...

But no, I encountered a really weird behaviour. See for yourself. I created a simple program periodically test sending 16 bytes. The OCTOSPI is set to transmit on 1 data line, data only, no instruction, no address.

 

Test A:

while (1)
{
HAL_Delay(1);
OCTOSPI1->DR = 0xFFFEFFFF;
OCTOSPI1->DR = 0x00010000;
OCTOSPI1->DR = 0x00010000;
OCTOSPI1->DR = 0x00010000;
}

Result: The idle level is High:

DS0002.png

 

Test B:

while (1)
{
HAL_Delay(1);
OCTOSPI1->DR = 0xFFFEFFEF;
OCTOSPI1->DR = 0x00010000;
OCTOSPI1->DR = 0x00010000;
OCTOSPI1->DR = 0x00010000;
}

Result: The idle level is Low:

DS0001.png

 

The difference between A and B is one bit: the MSB of the lowest byte of the first write. It is the first transmitted bit, if I understand correctly.

 

Can somebody explain this? How can that bit affect the idle level?

I think I'm missing something substantial here.

10 REPLIES 10
LCE
Principal

This OCTOPUSPI peripheral is a real beast.

That's a good one! :D