About Gabriel_Csefalvay

Gabriel_Csefalvay · 2024-04-04

Hi, Community,I'm trying to understand the OCTOSPI peripheral on my STM32L4P5. I'm new to STM32, but old in embedded. Particularly, I need to know/affect the idle level of the data line of the OCTOSPI. I thought that the last transmitted bit would re...

Gabriel_Csefalvay · 2024-04-10

@LCE wrote:Maybe the regular SPI peripheral might be better suited, a timer in PWM / DMA mode is probably too slow.What is the maximum bit rate you need?For generating 1080p@60Hz video, I'd need 150Mb/s. That should be doable with the double data rat...

Gabriel_Csefalvay · 2024-04-10

@KDJEM.1 I can check, just tell WHEN to check. After the 4 bytes sent? NOTE that I'm NOT reading anything from any external device. I don't think we get each other, maybe read my original post once more. By writing 1 word to the DR register, the FIFO...

Gabriel_Csefalvay · 2024-04-04

So far I found out that writing 8 words of 0x00000000 (32 bytes total) to the DR (data register) resets this behavior, which just happens to be the FIFO buffer size. A coincidence? :]

Gabriel_Csefalvay · 2024-04-04

@KDJEM.1 , thanks for the suggestions. A quick test shows that the SSHIFT and DHQC bits don't affect this behavior.I have read the OCTOSPI section of the errata sheet, but it says nothing about tx. Note that I use the OCTOSPI only for tx, I don't rea...

Gabriel_Csefalvay · 2024-04-04

unless you want to abuse it for something else. That's exactly what I want. :D I want to generate a VGA video signal, that's why I don't need the clock and why I need control over the idle level. Here is all the configuration code:OSPIM_CfgTypeDef OS...

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OCTOSPI line idle level - Weird behaviour

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