NUCLEO-H723ZG BOARD ADC NOISE
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‎2025-03-13 10:37 AM
Hi, I am planning on using STM32H723ZGT6 chip on one of my boards. I got the NUCLEO-H723ZG to measure the 12-bit ADC noise. From the datasheet for STM32H723ZGT6, the max ADC noise should be 5 times the LSB or 4.02mV. (1 LSB = 3.3/4096)
I am getting 22.5641mV of noise. Which is more than 5 times the max ADC noise from the datasheet. Below is an image of the data. I didn't use any averaging. I used a 1.5V battery as my ADC input.
I am wondering if this is expected ? I want to have 2 or 3 bits of noise on my board. Based on this, it seems I would be getting 5 bits of noise? Thank you!
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ADC
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STM32H7 Series
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‎2025-03-13 11:26 AM
The Nucleo boards aren't optimised for analogue ...
A complex system designed from scratch never works and cannot be patched up to make it work.
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‎2025-03-13 12:23 PM
The STM32 Nucleo board's power supply may be noisy due to USB or switching noise from the onboard LDO/Switching Regulator. Add capacitors (10uF + 100nF) near VREF+ and ADC inputs.
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‎2025-03-17 10:10 AM
Hi Andrew, I was wondering if there were any reference designs or internal configuration of the chip for best ADC noise performance. I did my my design with capacitors (10uF + 100nF) near VREF+ and ADC inputs as mentioned below by ahsrabrifat. I also followed Application note AN2834 for best results and my results are the same as NUCLEO-H723ZG Board, namely 5 bits of ADC noise. If there are any reference designs to best improve my ADC noise it would be very helpful!
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‎2025-03-17 10:34 AM
The best option is to do oversampling.
What is sampling rate required? How you drive inputs of the adc?
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‎2025-04-01 3:58 PM
Hi Master T, thank you for the response. We don't want to do oversampling so we are not slowed down. I am running the ADC clock frequency at the max, namely 75MHz.
Is there anything else you recommend?
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‎2025-04-01 4:22 PM
I get lower noise in the analog domain ( adc + dac ) on my nucleo-H743zi2 if I completely switched off Ethernet.
I find out, that even I don't use E-net anywhere in the project, no do any config - assuming all hardware circuits should stay in sleep mode : it's not a case with nucleo-144 E-net equipped. LAN8742A-CZ-TR is always running and generates huge power spikes.
To solve issue desolder L1. Also remove jumpers listed in table 13.
Another things to keep under control is clock. Has to be crystal - precise, not use any HSI. In case ST-Link provided, reconfigure to 25 /3 MHz, or it's generated by HSI in the ST-Link itself.
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‎2025-04-02 12:28 PM
Are you using the internal VREF or an external VREF? Maybe plot the VREF along side your sample data.
