How is SCLH and SCLL calculated in I2C_TIMINGR?

[SHU.1]

I have read the document RM0433 and AN4235, but the calculation is still a puzzle.

For example, if my

I2C frequency = 1MHz,

I2C clock source frequency = 170MHz,

AF=on, DF=off,

rise time = 80ns,

fail time = 10ns,

how do you get the SCLH = 0x10 and SCLL = 0x31?

Why is low period 3 times as long as high period?

I would like to use SCLH to increase the high clock period, as it is at the edge of the spec. It is not clear what parameter I shall change to increase SCLH.

Thanks.

[Sarra.S · Accepted solution]

Hello @SHU.1​ and welcome to ST Community,

As mentioned in the AN4235, SCLH and SCLL values depend on the rise and fall time

• SCLH = (I2C clock source frequency / (2 * I2C frequency * (Rise time + Fall time))) - 1
• SCLL = (I2C clock source frequency / (2 * I2C frequency * (Rise time + Fall time))) - 1

with your values :

• SCLH = (170 MHz / (2 * 1 MHz * (80 ns + 10 ns))) - 1 = 16 = 0x10
• SCLL = (170 MHz / (2 * 1 MHz * (80 ns + 10 ns))) - 1 = 49 = 0x31

>>Why is low period 3 times as long as high period?

The duty cycle of the clock signal is SCLH / (SCLH + SCLL) = 16/(16+49) = 0.25

which means the clock will be high for 25% of the time and low for 75% of the time

Hope that helps!