Posted on August 16, 2017 at 16:05Ok,
sorry for the code above, it is not mine (copied from the internet).
Mine looks like this and doesn't work as well. And I can't understand why... the green LED LD2 is working on the board.
#include 'stm32f4xx.h'
void SystemClock_Config(void); //function prototype for SystemClock configuration
void GPIO_Config(void); //function frototype for GeneralPurposeInputOutput configuration
int main(void)
{
//initialization
SystemClock_Config();
GPIO_Config();
int n;
while(1)
{
GPIOA->ODR |= 0x20;
//for(n=0; n<5; n++);
GPIOA->ODR &= ~0x20;
//for(n=0; n<5; n++);
}
}
//SystemClock configuration
void SystemClock_Config(void)
{
RCC->CR |= RCC_CR_CSSON | RCC_CR_HSEBYP | RCC_CR_HSEON; //clock security system enabled, HSE Enable Bypass and HSE Enable
//HSE Clock
while (!(RCC->CR & RCC_CR_HSERDY)); //wait till HSE oscillator is stable
//FLASH Configuration
FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; //FLASH Prefetch, Instruction, Data Cache enable;
//FLASH wait states 3 !change to higher value, if problems occur
//PLL configuration and activation
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC_HSE | RCC_PLLCFGR_PLLM_4 | 0x00000078 | RCC_PLLCFGR_PLLP_0;
RCC->CR |= RCC_CR_PLLON; //activate PLL
while(!(RCC->CR & RCC_CR_PLLRDY)); //wait till PLL is stable
//Sysclk activation
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
RCC->CFGR |= RCC_CFGR_SW_PLL;
while (!(RCC->CFGR & RCC_CFGR_SWS_PLL));
//PPRE1 and PPRE2 Prescaler
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; //HCLK divided by 4
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; //HCLK divided by 2
}
//GeneralPurposeInputOutput configuration
void GPIO_Config(void)
{
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN; //enable AHB1 GPIO->A and GPIO->C clock
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
RCC->AHB1RSTR |= RCC_AHB1RSTR_GPIOARST | RCC_AHB1RSTR_GPIOCRST;
GPIOA->MODER |= GPIO_MODER_MODER5_0;
}
Whats wrong with mine?
