Multiple Slaves Connected to SPI3 in master mode, Fails

[TShet]

Hi,

We designed stm32f7 based custom board and it consist 3 slave devices (FPGA) connected to SPI3 in master mode. when three slaves connected simultaneously & try to access one by one, first two slaves are able to read/write & 3rd slave fail to access (read/write)

But if i connect one by one device to SPI at a time, it works as expected without any errors.

Is there any know issue/bug with SPI3, when we interface more than two slaves ?

[berendi]

No.

The SPI controller neither knows nor cares how many slaves are there.

[TShet]

Then can you hint, what could be causing issue ?

[Tesla DeLorean]

Your question is a bit sparse on implementation detail. Present better.

I'd guess the slaves aren't tristating​ the output properly, the load is too high, or some other issue with clock or data lines and timing. Look at selects and data/clocks on a logic analyser to better understand the mode of failure / "not working".

[TShet]

Thanks for response,

We probe in the scope and found that, when try to access third slave, there is no SPI clock output from STM, we still investigating... what will makes clock to stop ?

[waclawek.jan]

> what will makes clock to stop?

Misconfigured SPI or GPIO

Read out SPI and GPIO registers content and check/compare to working case.

JW

[berendi]

Or no data written into the data register

[TShet · Accepted solution]

Sorry for the late response,

We found the issue, the root cause is after programming each FPGA, it will pull the MOSI line to Low. After 2 FPGA program, the pull is very strong and not allowing to program 3 FPGA

We corrected in FPGA, Now no pull in FPGA and able to program all three and as well communicate