Missing section IRTIM in STM32U0 RM and more.

AA1 · ‎2024-04-26

1. According to datasheet, STM32U0 family have an IRTIM (Infrared interface). But this section is missing in RM0503. Also in SYSCFG_CFGR1 there is missing IR_MOD and IR_POL bits.

2. In RTC section Figure 297 it is missing RTC_OUT2 and RTC_REFIN pins. See same block for STM32G0 family.

3. In RM0503 section NVIC table 54, I think that PVD_PVM should be PVD / PVM. Also ADC_COMP should be ADC / COMP. WWDG should be WWDG / IWDG. TIM6_DAC / LPTIM1 should be TIM6 / DAC / LPTIM1.

4. Usually each section name ends with an abbreviated name in parenthesis. Ex: Low-power universal asynchronous receiver transmitter (LPUART). And this abbreviated name is also in bookmarks on the left size of each RM. But (LPUART) is not in bookmarks in several RM possible all from the beginning.

STTwo-32 · ‎2024-05-06

All those issues have been escalated for correction under internal ticket number 180725. Thank you so much for your help. For the name on the bookmarks, it seems to be fine on my side:

Best Regards.

STTwo-32

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AA1 · ‎2024-05-10

Hello,

I have more.

1. STM32U0 RM page 135:
1. Available on STM32U0 devices only.
should be:
1. Available on STM32U0x3xx devices only.

2. STM32U0 have 3 to 5 tamper pins. But datasheet table 3 and RM table 22 only mentions 2 pins for all cases.

3. For STM32U0 after reset system clock is MSI 4 MHz. But in some pages as RM page 163 it is HSISYS. RM page 168. "When leaving the Stop 0 or Stop 1 modes, HSISYS ..."- But clock is MSI and not HSISYS. RM page 175: The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop. But 000 is MSI clock. And I believe that there are more references to HSISYS that should be MSI.

4. STM32U0 doesn't have backup SRAM, only backup registers. But backup SRAM is mentioned several times in AN5938. Also TAMP_OUTx pins is mentioned in AN5938 and I believe they doesn't exist.

5. In AN6091 table 22 is missing SPI2 and I2C4 addresses. Also in table 24: WWDG -> WWDG / IWDG, ADC_COMP -> ADC/COMP. In table 34: I2C Instances are 4 for STM32U0x3xx and not 3.

6. RM page 166: For TIM15 ... should be For TIM16...

7. RM LCD section page 438 bottom: "Three different clock sources ...". But only are listed two. Missing clock HSE/32. And in page 452: Depending on the product implementation, all these interrupts events can either share the same interrupt vector (LCD global interrupt), or be grouped into two interrupt vectors (LCD SOF interrupt and LCD UDD interrupt). Refer to the (missing doc name) for details.

Algo there is only LCD global interrupt in vector table. I believe that there is only one interrupt vector for this product

8. STM32U0 SPI doesn't have I2S mode. But RM page 1185 talks about it. It have I2SE and ASTRTEN bit that I believe doesn't exist.

9. STM32U0 FLASH row size is 256 bytes. But in RM page 72 step 6 have:

6. Write 16 double-words to program a row (128 bytes).

This should be:

6. Write 32 double-words to program a row (256 bytes).

10. Just a detail, but in RM MCO and MCO2, should be to be MCO1 and MCO2.

And now the bookmarks is ok.

Best regards,

AA1 · ‎2024-05-10

I forgot this to add to 9.

Algo in page 72 bottom, "16 double words" should be "32 double words". And in page 89 bottom, "16 double words (128 bytes)" shoudl be "32 double words (256 bytes)".

And just other detail: I2C_ISR bits TXIS and TXE are of type "r" and not "rs".

Did you see the other issues like missing I2C4 hardware address?

Best regards,

AA1 · ‎2024-05-13

Hello,

It seems that there is also an issue in text "backup SRAM" in STM32U0 RM. Search for this text. I found at least it in tamper detection section, FLASH_OPTR and SYSCFG_CFGR2 registers. It seems that "backup SRAM" is SRAM2 and without backup.

Best regards.

STTwo-32 · ‎2024-05-21

Hello @AA1

Thank you so much for your help. All your remarks have been escalated to the concerned team for correction.

Best Regards.

STTwo-32

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AA1 · ‎2024-05-21

Hello,

I have more.

1. AN5938 page 15:
"Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, 1 MHz, 2 MHz, 4 MHz (default value), 8 MHz, 16 MHz, 24 MHz, 32 MHz, and 56 MHz".
Here 56 should be 48

2. RM page 176: "The software must set this bitfield so as not to exceed 54 MHz on this clock."
Here 54 should be 56.

3. RM page 168:
"When leaving the Stop 0 or Stop 1 modes, HSISYS becomes automatically the system clock.
When leaving the Standby and Shutdown modes, HSISYS (with frequency equal to HSI16) becomes automatically the system clock".

Missing Stop 2 mode and the clock is not HSISYS. Clock is selected by STOPWUCK bit and can be MSI or HSI16.

4. RM page 159: The HSISYS clock derived from HSI16 can be selected as system clock after wake-up from Stop modes (Stop 0 or Stop 1).
Should be:
The HSI16 can be selected as system clock after wake-up from Stop modes (Stop 0, Stop 1 or Stop 2).

5. RM page 166: "This function remains available in Stop 0, Stop 1 and Standby modes".
Missing stop 2 mode.

6. RM tables 92, 197 and 208
Missing stop 2 mode. As stop 2 mode is a new mode it is missing in some cases.

7. RM0031 page 363:
0: Off - OC1 is not active. OC1 level is then a function of the MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
I think this should be just:
0: Off - OC1 is not active.

8. RM page 109: In Standby mode step is repeated. The second should be deleted

9. RM page 61: TIM1/15 should be TIM1/15/16.

10. As there exists LSECSS, HSECSS* is a better name for CSS on HSE. And this name is used in some RMs.

12. RM table 178 word BKPRAM. As I said before, STM32U0 doesn't have backup SRAM. At least I think this.

13. Which is the clock when CSS on HSE failure is detected?
See STOPWUCK bit. Clock can be MSI or HSI16
But CSS section doesn't talk about this bit. STM32H5 RM talks.

14. For STM32U0, USB RAM is 1K. But on some pages it appears as 2048 bytes. For STM32G0 it is 2K. Also as "USB RAM2" doesn't exist, "USB RAM1" should be "USB RAM". But this is just a detail.

15. DS talks about "Batch acquisition mode (BAM)". What is this? I didn't find this in RM. Maybe this is used with ADC.

Best regards,

AA1 · ‎2024-05-22

Hello,

Several EXTI lines in vector table don't are according to table 58.
For example: RTC and TAMP interrupts (combined EXTI lines 19 & 21)
Should be:
For example: RTC and TAMP interrupts (combined EXTI lines 28 & 29)
RM page 164: CSSI should be CSSF and LSECSSI should be LSECSSF.

Best regards,

AA1 · ‎2024-11-26

I found more issues.

RM page 163: register RCC_ICSCR should be replaced by registers are RCC_CR and RCC_CFGR.
Page 163: TIM17 should be removed because it doesn't exist.
Page 170: CEC should be removed because STM32U0 doesn't have HDMI-CEC.
Page 162: LSEBYP and LSEON bits don't are in RCC_AHBSMENR register but in RCC_BDCR register.
Page 209:MSISRANGE[3:0] is always 0100. Should be 0100, 0101, 0110, 0111.
Page 171: RCC_CSR reset value should be: 0xXX00 0600.
Page 57, table 2:
0x2000 0000 - 0x2002 9FFF
should be:
0x2000 0000 - 0x2000 9FFF
0x2002 A000 - 0x3FFF FFFF
should be:
0x2000 A000 - 0x3FFF FFFF
DS page 9: Missing "I2C3 on pins PB3/PB4" as boot device. See AN6091 page 10.
RM page 67: "After power reset, the HCLK clock frequency is 16 MHz ..." This is wrong because reset clock is MSI 4 MHz.
Page 701: ITR4..ITR8. Where are them? Also ITR3 is always empty on page 702, table 133.
Page 248: Missing IWDG bit in SYSCFG_ITLINE0 register
Page 254: TIM1_CCU should be TIM1_COM.
Pages 101 and 102: HDP1_PEND[7:0] should be HDP1_PEND[6:0]
Page 86: FLASH_ACR reset value should be 0x0004 0200 and not 0x0004 0600.

And some of this issues are also in STM32G0 RM.

STM32F0 RM page 184: Missing SYSCFG_ITLINE31 with USB