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Sachin Sanghani
Associate
March 15, 2021
Solved

Micron QSPI Nonvolatile Config register Write not working.

  • March 15, 2021
  • 2 replies
  • 1833 views

Hi Everyone, I am using STM32H757I-EVAL board and the onboard Twin Quad SPI Nor Flash ( MT25QL512ABB8ESF-0SIT ). I have configured QSPI to operate in DUAL Flash mode.

I am able to perform memory read, memory write, memory erase, and internal configuration register read operation from/to QSPI flash.

But, When I try to update NonVolatile configuration register, It fails to update it.

If I change my QSPI memory configuration from Dual Flash mode to Singal flash mode, It works for Flash-1.

So, Is there anything that I am missing for the Dual Flash Mode?

I am enabling Write Latch before write Operation.

As per the technical notes for STM32H757i_EVAL board, both flash needs to have an ideal configuration.

Here is the code snippet

int32_t WriteNonVolatileConfigurationRegister( QSPI_HandleTypeDef *Ctx, Interface_t Mode, uint8_t *pData )
{
 QSPI_CommandTypeDef s_command;
 
 /* Initialize the command */
 s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES;
 s_command.Instruction = WRITE_NONVOL_CFG_REG_CMD;		// 0xB1
 s_command.AddressMode = QSPI_ADDRESS_NONE;
 s_command.DataMode = QSPI_DATA_4_LINES;
 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
 s_command.DummyCycles = 0;
 s_command.NbData = 4;	// QSPI_DUALFLASH_ENABLE = 0x04, QSPI_DUALFLASH_DISABLE = 0x02
 
 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
 
 /*write enable */
 if( WriteEnable(Ctx, QPI_MODE)!= OK)
 {
 return ERROR_COMMAND;
 }
 
 /* Send the command */
 if (HAL_QSPI_Command(Ctx, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
 {
 return ERROR_COMMAND;
 }
 
 if (HAL_QSPI_Transmit( Ctx, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
 {
 return ERROR_TRANSMIT;
 }
 
 /* Configure automatic polling mode to wait the memory is ready */
 if( AutoPollingMemReady(Ctx, QPI_MODE)!= OK)
 {
 return ERROR_COMMAND;
 }
 
 return OK;
}

This topic has been closed for replies.
Best answer by Sachin Sanghani

What Data? solved my issue!!!!

Expected Data is: { 0xF6, 0xF6, 0xFF, 0xFF }

Can write NonVolatile Config register !!

Thanks for your Question :)

2 replies

Tesla DeLorean
Guru
March 15, 2021

And how's this called? What data? Does it wait on both devices? Does the Write Enable get to both?

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Sachin Sanghani
Associate
March 15, 2021

Hi @Community member​ , Thanks for looking into this issue.

Does the Write Enable get to both?

-> Yes, The WriteEnable will set Write enable latch on both devices.

Does it wait on both devices?

->Yes, The AutoPollingMemReady will poll Write in progress bit from Flag Status register on both devices.

What data?

-> NonVolatile Configuration register is a 2Byte register, and I want 0 and 3rd bit to be zero ( default all bits are set to 1). So my data buffer is { 0xF6, 0xFF, 0xF6, 0xFF }

"The WRITE NONVOLATILE CONFIGURATION REGISTER operation must have input data starting from the least significant byte."

And how's this called?

-> This will be called by main.

WriteNonVolatileConfigurationRegister( &hqspi, QPI_MODE, nonVolatileConfigurationRegBuf );

uint8_t nonVolatileConfigurationRegBuf[4] = { 0xF6, 0xFF, 0xF6, 0xFF };

Sachin Sanghani
Sachin SanghaniAuthorBest answer
Associate
March 15, 2021

What Data? solved my issue!!!!

Expected Data is: { 0xF6, 0xF6, 0xFF, 0xFF }

Can write NonVolatile Config register !!

Thanks for your Question :)

Tesla DeLorean
Guru
March 15, 2021

Yes, data should be interleaved

Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..