One user mentions noise from USB
https://community.st.com/s/question/0D50X00009XkfMDSAZ/stm32f4-adc-noise-with-increased-activity-in-usb-fs
Other comments:
Keep the wiring short, and make sure the resistor value matches the ADC input impedance. I’ve successfully used values between 2k and 10k. The higher the impedance and the longer the wires, the more susceptible to EMI.
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When the ADC samples the input voltage, a sample and hold capacitor is charged up. The signal current during this time can cause the observed �?noise�? when the signal source is not of low impedance. Try increasing the sampling cycles.
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In STM32F427?the ADC noise is horrible when the mcu access the sdram or fpga by fsmc at the same time.
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Instead of the STM32 internal ADC, I used an ADS7822 12-bit SAR ADC from Burr-Brown. Ratsnested on the same board with filtering as described in my previous posts. Performance is excellent, < 1.5 bit noise. I conclude that in practice it is not possible to use the STM32 internal ADC at its advertised resolution, at least in packages where VREF+ and VREF- are inaccessible.
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the most likelu cause is the return of your filter capacitor/the return of your input. I forgot to mention, ground is not ground. a wire is not a wire.
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I would recommend to buffer with a fast and precise OP.
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see STM application note AN2668 page 9! �?Improving STM32F101xx and STM32F103xx ADC resolution by oversampling�?. STM has done a similar thing: 1.65V gave 2050count, min was 2034 max 2076. my conclusion is: never rely on a single AD result in your application if you need more than 8bit of precision. (PID control / if else decision etc)
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My conclusion is this: there must be spurious charge shots out of the ADinputs. Quite rare, but if they hit the right timing, an attached condenser stores it, and corrupts the result.
1) With averaging / digital filtering you can eliminate these spurious results. Extreme values are very rare.
2) Do not use condensers on STM AD inputs.
I have more than 20years experience with embedded measuring systems / analogue front ends. These effects are not there in 8051 derivates that I know, ATMEGA, PICs, also not on Stellaris Cortex M3 devices.
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you, evidently believe the ground plane is ground IT IS NOT. make the input (or experimental resistors) connect no more than 0.5 cm from Agnd. your readings of 3V3 are correct, it jives with typical jitter on a supply rail.
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I doubt that on 3 different types of eval boards the reason is always poor grounding. I rather suspect a poor silicon mask design on the F100 family. Maybe the ones with an external reference pin show better results.
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Others seem to have come across this issue: ADC glitches (2nd page), they could actually see glitches with the scope. I had done more tests by changing the return path of the condenser directly to AVSS, instead 26counts, I achieved 20counts. Still way too much.
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It is mixture of the sampling time and external Capacitor issue!! The side effect of any SAR ADC is that the sample capacitor within the ADC is directly charged by the external signal, that means if the sample time is insufficient, then the charge left on the sample capacitor by the previous conversion of a channel can affect the accuracy of the channel currently being converted. Generally, some users place a large capacitor “Cext�? (100nF ) from the ADC pin to ground, This capacitor is used to lower the source impedance of the channel as seen by the ADC so that the internal sample capacitor can be charged quickly. But this will create a charge-sharing process between Cext and Cs, whose RC time constant is primarily determined by the maximum ADC input resistance (1KOhm) and maximum sample capacitance (8pF) of the ADC.
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https://community.st.com/s/global-search/stm32%20adc%20noise
