low lever driver backup sram example

[Evan .1]

Is there an LL example to enable the backup ram.

This doesn't work:

   // Enable PWR clock

   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);

   // Enable Backup ram clock

   LL_APB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_BKPSRAM);

   LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB);

   // Enable backup ram regulator

   LL_PWR_EnableBkUpAccess();

   LL_PWR_EnableBkUpRegulator();

   while (LL_PWR_IsActiveFlag_BRR() == 0);

   *(__IO uint32_t *) (BKPSRAM_BASE ) = 0x5A5A5A5A;

I can't find in the documentation what I forgot.

Thanks.

[Adam Santamaria]

Hello,

I don't know which product you are using precisely.

But the STM32CubeF7 package proposes the Example RTC_Tamper with the following purpose: "Configuration of the RTC HAL API to write/read data to/from RTC Backup registers."

You can download the package here:

https://my.st.com/content/my_st_com/en/products/embedded-software/mcu-mpu-embedded-software/stm32-embedded-software/stm32cube-mcu-mpu-packages/stm32cubef7.html

It is available for the boards STM32756G_EVAL, STM32F769I_EVAL, STM32F746ZG-Nucleo but there should be no problem to adapt it for your F7.

The example path is for example STM32Cube_FW_F7_V1.16.0\Projects\STM32756G_EVAL\Examples\RTC\RTC_Tamper

Hope it will help.

Adam S.

[Evan .1]

I'm using the Nucleo-F676ZI

                          LL_PWR_EnableBkUpAccess();

                          LL_RTC_BAK_SetRegister(RTC, LL_RTC_BKP_DR1, 10);

Power Cycle:

uint32_t data1 = LL_RTC_BAK_GetRegister(RTC, LL_RTC_BKP_DR1);

works fine. So this that is not the problem and the backup supply and regulator works correctly.

   LL_PWR_EnableBkUpAccess();

   for(i=0;i<10;i++)

   {

      *(__IO uint8_t *) (BKPSRAM_BASE+ i) = i;

   }

   SCB_CleanDCache_by_Addr ((uint32_t *)BKPSRAM_BASE, BKPSRAM_SIZE);

In memory browser I see the memory is correctly written. After a reset cycle I can read the data correct back.

Only after a power cycle all the data is lost.

I excluded CPU_CACHE_Enable from my program. I use the default LL driver STM32F767ZITX_FLASH.ld and initialization functions.

So some detailed information how to use the Backup ram or a backup ram example should be nice.

Thanks!

[waclawek.jan]

> In memory browser I see the memory is correctly written.

On what address?

JW

> I'm using the Nucleo-F676ZI

A new model, yummy! ;)

[Evan .1]

Nucleo-F767ZI

#define BKPSRAM_BASE          0x40024000UL /*!< Base address of : Backup SRAM(4 KB)                                                    */

from stm32f767xx.h

[Evan .1]

Write backup ram

reset.

Breakpoint after enables breakup sram clock

Power cycle.

Again breakpoint after enabling breakup sram clock

[waclawek.jan]

Humm, and PWR_CSR1 content at both of these situations?

Also, RTC runs uninterrupted during the power outage, i.e. if it's say a minute long, the RTC time is not delayed?

JW

[Evan .1]

PWR_CSR1 is in both situation 0x34000.

I don't use the RTC. I only need the backup ram.

[Adam Santamaria]

Hello,

So it seems that there is a problem with this part of your code:

LL_PWR_EnableBkUpRegulator();

while (LL_PWR_IsActiveFlag_BRR() == 0);

Because bit 9 (BRE Backup regulator enable) of PWR_CSR1 is not setif its value is 0x34000.

PWR-CR1 should be 0x34200 even after a power cycle

Could you try to set it manually with PWR->CSR1 = 0x00034200,

And check that bit 9 has not been reset after power cycle ?

[Evan .1]

   PWR->CSR1 = 0x00034200;

don't change the value of CR1 after this the value is still 0x34000

I also tried this:

   LL_PWR_EnableBkUpAccess();

   PWR->CSR1 = 0x00034200;

Still the CR1 is not updated.

[Adam Santamaria]

The following code works for me (i used the f746 discovery board but the register mapping is the same for f76x products).

PWR->CR1 is well updated after the while (test is a global variable).

RCC->APB1ENR |= 0x10000000;

 PWR->CR1 |= 0x00000100;

 RCC->AHB1ENR |= 0x00040000;

 test = PWR->CSR1;

 PWR->CSR1 |= 0x00000200;

 while( (PWR->CSR1 & 0x00000008) != 0x00000008) ;

 test = PWR->CSR1;