L0 I2C slave RX DMA - clean cancel with I2C STOP ?

[LCE]

Heyho,

using L073 at 32MHz, so even I2C transfers "seem" fast, at least in "fast mode plus" at SCL 1 MHz. And I don't want to over-use clock stretching.

I'm looking for a way to use I2C slave receive with DMA, but an unknown transfer length.

Right now it looks to me as if I could do the following:

• I2C & DMA prep: all stuff & addresses set, DMA in I2C enabled
• on I2C ADDR match interrupt:
  • set DMA CNDTR to max buffer length
  • enable DMA 
• on I2C STOP match interrupt:
  • disable DMA

Any problems with that?

Have only 1 device for now...

Thanks!

[LCE · Accepted solution]

Working nicely!

The I2C slave's DMA RX is set to maximum buffer size, when an I2C bus STOP (funny wording) is found a flag is set in the I2C IQR, which is then checked by the I2C control function.
This compares the first received data byte ( = I2C packet length) in the DMA RX buffer with the CNDTR register, which should be buffer max - rx length.

But boy, there were some *** mistakes on my side, mostly with the I2C TX test function in the same MCU with another I2C peripheral (e.g. forgot to clear NBYTES in CR2). 

And 2 big things I found in the L073 errata (2.12.9 Transmission stalled after first byte transfer).
The other one the minimum clock requirements.

With DMA this seems to run smoothly at CPU clock 32 MHz (L073 max) even in "Fast Mode Plus" (1Mbit) - for now...