IWDG (Watchdog) Enable on STM32

[Damiano Balzani]

Posted on February 02, 2018 at 09:21

Hi everybody,

i'm tryng to configure the IWDG but it doesn't work. i didn't find the enable bit, is there?

Can you help me?

I post my code here

void wdt_enable(void)

{ RCC -> CSR = RCC -> CSR | 0x00000001; //Enable LSI Clock while((RCC -> CSR & 0x02)==0) { //add timeout code here } IWDG -> KR = 0x0000CCCC; //Enable IWDG IWDG -> KR = 0x00005555; //Enable register access IWDG -> PR = 0x010; //Set Prescaler /16 IWDG -> RLR = 0xFFF; //Set Reload Value for 2.048 seconds while(IWDG -> SR) //Check if flags are reset { //add timeout code here } IWDG -> KR = 0x0000AAAA; //Refresh the counter}

Thanks in advance

Damiano

#stm32-iwdg #iwdg

[henry.dick]

Posted on February 02, 2018 at 13:49

'

i didn't find the enable bit, is there?'

have you read the code you have written? it explicitly does so.

[waclawek.jan]

Posted on February 02, 2018 at 13:56

it doesn't work

How do you know?

i didn't find the enable bit

There is no enable bit - writing the key value CCCCh starts the watchdog

JW

[Damiano Balzani]

Posted on February 02, 2018 at 14:04

because i'm using a debugger and i'm seeing that the registers have not the value written in the code

do i miss something?

Thanks

DB

[henry.dick]

Posted on February 02, 2018 at 14:09

'because i'm using a debugger and i'm seeing that the registers have not the value written in the code'

that's a different question.

'do i miss something?'

read the datasheet, as it is designed to answer this sort of questions: it has a section specifically on that. 

[waclawek.jan · Accepted solution]

Posted on February 02, 2018 at 14:09

Which register?

IWDG_KR is write only, ie. reading it back is not defined (probably results in 0).

IWDG_PR and IWDG_RLR have this note - read the IWDG chapter in RM:

Note: Reading this register returns the reload value from the VDD voltage domain. This value

may not be up to date/valid if a write operation to this register is ongoing on thisregister. For this reason the value read from this register is valid only when the RVU bitin the IWDG_SR register is reset.

JW

[Damiano Balzani]

Posted on February 02, 2018 at 14:33

Thanks for the help. I didn't read it!

Sorry for my mistake

Damiano