IWDG timing issues on STM32F205RBT7 – Suggestions needed for reliable watchdog behavior

[Nitin]

Hello ST Community,

I’m working on a project using the STM32F205RBT7 and planning to integrate the Independent Watchdog (IWDG) for system recovery. However, I’ve encountered significant timing inconsistencies across multiple boards (tested on at least 4 custom and EVK boards). For example, when configuring a 125 ms timeout, the watchdog sometimes triggers as early as 120 ms and other times as late as 140 ms.

This variability in the IWDG timeout raises concerns for time-critical applications. Has anyone else observed such behavior with the IWDG on this MCU?

I’d appreciate any suggestions for improving timing reliability, or if switching to WWDG or a software-based watchdog might be better. My only hesitation with WWDG/software watchdog is their dependency on SYSCLK, which may not be fail-safe in certain failure conditions.

Thanks in advance for your insights and recommendations.

[TDK]

The IWDG is clocked by the LSI, which is not particularly accurate. There's no magic solution for this--you get what you get. You could measure the clock rate at startup and set IWDG based off of that, but that seems prone to mistakes and other issues.

If waiting a few more ms to reset is an issue, of if you need the reset to occur at a specific time, then switching to WWDG (clocked from PCLK1) is an option.

Consider using the clock security system (CSS) if you are concerned about the HSE clock failing. The system can fall back to using HSI clock.

[Sarra.S]

Hello @Nitin, 

Check this post: IWDG findings - STMicroelectronics Community