Is there any way to delay read timing of SPI of DFSDM in STM32L4?

[KenjiEdo]

あなた:

Hi, I'm developing audio recording system uinsg DFSDM of STM32L4. The microphone sound is converted to digital by external ADC and the converted data is sent via SPI to DFSDM. The problem is that the external ADC provides data but it has setup delay from rising edge of CKOUT and the data for DATIN isn't available at the time of riging edge of CKOUT. Is there any way to delay read timing of SPI so that it can wait setup delay? The setup delay of external ADC is about 58ns. 

[ELABI.1 · Accepted solution]

Hi @KenjiEdo,

I don't have any idea about the audio, but I suggest using a timer that triggers on the rising edge of CKOUT to start. It will wait for 58 ns, then trigger an action to read the ADC data (after 58 ns, the data is ready).

Thank you.

ELABI.1

[KenjiEdo]

Hi ELABI.1, thank you for your feedback.

In my understanding, the timing of SPI data read is combined with rising edge / falling edge of CKOUT within DFSDM functional block and we can't configure timing of SPI read after our own timer which is triggerd by rising edge. I'm afraid your suggestion might be difficult. I have tried to read data at the falling edge of CKOUT and fortunately we can read the data correctly. I assume this is because the ADC data remains for a while. Of cource this isn't good soution but it will be a kind of workaround solution. Thanks.