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Is there any upper limit of SPI devices on a single interface? Demultiplexer SPI CS?

Associate II

I would like to connect 4 devices on two interfaces or 8 on one SPI bus and I would like to make sure that it will be working properly (given that parasitic capacitance will be small enough). I will be using STM32L496ZGT. I would like to ask also, what is your best way of handling multiple chips select signals (for eg. 8)? Is using demux a good idea?


A 3-to-8 or 4-to-16 type decoder, with an enable, or unconnected idle state would be how I might approach.

Watch that the SPI slave does actually disassociate from the bus when it's CS is HIGH.

Watch timing expectations.

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Thank you very much for your reply. The decoder might be a better idea. I also have a few spare pins on MCU, so the decision lies in the efficiency of both solutions. Maybe do you know how industrial-grade solutions are sorted in such situations? Is simple better in this case?


If bus capacitance is out, it depends on the bus topology. As multi drop multi NSS, it should be ok. As daisy chained, the last slave will accumulate a MISO delay vs STM32 sck which will limit the max operating frequency. Otherwise, as most SPI have multiplr pins for easi SPI signals, you can create 2 buses with 1 HW SPI by dynamically changing alternate function from gpio to spi mode as it is time multiplexed.

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