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Is there any case that framing error in UART communication can cause delay in detection of next byte?

kkoutso
Associate II

I have a strange situation with my implementation that in all other cases runs smoothly, tested with baud rates up to ~250K. During an interaction with a specific peer that is instructed to reset, a framing error is detected when this peer reappears on the line. This is detected as input 00 with Framing Flag raised. The next byte, around 40ms later, seems to be captured half correctly. Meaning that although expected as 0x52, the input is read as 0xF5. Taking into account that the transmission on uart is taking place LSB first, it gives me the impression that the lsb part (0100) is lost and start bit is detected just before the last bit (0) of this part, so that 1010 (5) is considered as the LSB part of the byte and the following high status of the line is considered as the MSB part (1111 or F) plus stop bit, which ends as 0xF5 in the RDR.

I think this one resembles this one.

4 REPLIES 4
kkoutso
Associate II

I have connected the RX line to an A2D pin and sampled the line to see what is the status before the 0x52 byte. The peer keeps the line in break (00) and toggles to 1 (idle) for ~10-20μs which seems not sufficient for STM32 to properly evaluate the falling edge for the start condition and ends up "reading" the 2nd bit (0100) as start condition. Does anyone have a clue on how to make STM USART able to detect such condition.

Which STM32?

Maybe it's easier to wait on the transmitter side a little bit longer after releasing the line, before starting to transmit. I doubt you can change the receiver's timing, it's most likely hardwired.

JW

The MCU is STM32G071KB.

I cannot depend on the tx side as it is an established device with which I should interface. I have probed the RX line with a USB2UART cable and this one is able to react properly to the short start condition and read 0x52 as expected.

You can try to disable UART, wait until the break end, and enable UART again.

JW