2022-09-01 07:46 AM
Hi, I have both rising and falling edge enabled for an EXTI interrupt on GPIO. I would like to know what edge the interrupt has been entered on, re-reading the GPIO line is error prone and not viable due to latency. I can have a counter that I check with "c & 1", but I'm worried about the initial state of the line which is unknown, this could break the "c & 1" logic.
Is there a correct way to find out the interrupt polarity, without additional reads of the interrupt line?
2022-09-01 08:04 AM
If you've got signals this flaky externally, buffer them.
Or use a TIM pin where the CH1 / CH2 trigger on upposing edges of the TIMx_CH1 input pin (CH2 can use via Indirect Mode, ie criss-cross of CH1<->CH2, and CH3<->CH4)
2022-09-01 09:59 AM
Thanks for the answer. The signal integrity is pretty good and not noisy, the edges are coming in pretty quick tho, rising edge followed by falling happens in a 16ns timespan. I need to decide if I need to change the MODE of both PortA and B. If another falling edge comes in I can keep MODE the same, if not I need to change it. I want to prevent reading GPIO pins because that adds about 40ns delay. The signal stays low for about 200ns in that time I also have to read ram and output to PortA and B. Unfortunately I can't use DMA to output on PortB as pin[0..3;9..12] of the B port are not accessible and I need to workaround that by having the CM7 shift the data. If there is some way to shift by 4 through DMA which I missed it would be awesome!
2022-09-01 10:47 AM
Definitely seems like something to be done via a CPLD and/or logic directly
Consider using BSRR rather than ODR if you need to scatter-shot a subset of GPIO within the bank
Things like FIFO memories can provide elasticity where there is some mismatch of rates, or burst behaviours.
2022-09-04 12:44 AM
or...connect input to 2 exti pins, set one to rising and other to falling edge.
then dont need to read state after trigger. :)
2022-09-04 12:50 AM
Makes sense if you have pins to spare :) Unfortunately not a possibility for me.
2022-09-04 01:26 PM
A TIM should be able to cross connect one pin to two channels via indirect mode.
2022-09-04 08:06 PM
What is a TIM and how much added latency are we talking about?
2022-09-04 10:59 PM
TIM -> timer