2018-08-14 11:53 AM
In the STM32l476, I have found that the VREFBUF_CSR
register 'HIZ' bit is being set from default 0 to 1 when SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) is executed. RCC_APB2ENR_SYSCFGEN is the LSB.
2018-08-14 02:57 PM
VREFBUF_CSR.HIZ is by default 1:
However, reading VREFBUF registers returns all 0 until VREFBUF clock is not enabled in RCC.
And it so happens, that VREFBUF shares its clock-enable bit with SYSCFG (and also COMP):
JW
2018-08-15 01:48 AM
Thank you https://community.st.com/s/profile/0050X000007vqmpQAA, I hadn't noticed the default setting of HIZ being 1 according to RM0351. Yes the value of VREFBUF_CSR is all zero at startup, and remains so until RCC_APB2ENR bit 0 is set.
2018-08-15 07:56 AM
So if this has been answered, please mark so. Thanks.
JW