In the STM32l476, I have found that the VREFBUF_CSRregister 'HIZ' bit is being set from default 0 to 1 when SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) is executed. RCC_APB2ENR_SYSCFGEN is the LSB.
Thank you https://community.st.com/s/profile/0050X000007vqmpQAA, I hadn't noticed the default setting of HIZ being 1 according to RM0351. Yes the value of VREFBUF_CSR is all zero at startup, and remains so until RCC_APB2ENR bit 0 is set.
