Is it possible to have interrupt (TIM1_UP_TIM16) fire only once per cycle in centre aligned mode ?

[MMeva.1]

Hello,

I am using STM32F100RBTx device present on STM32VLDISCOVERY board.

I am using TIM1 with the configuration listed below. Please note that this is a partial config, other channel and clock related settings are irrelavant to interrupt so I havent posted.

cr1.ckd = 0;

cr1.arpe = 1;

cr1.cms = 2;

cr1.urs = 1;

dier.uie = true;

Interrupt vector : TIM1_UP_TIM16

With this I am able to generate centre aligned PWM waveforms with proper duty and frequency, but the interrupt is triggered twice in each cycle, one when the CNT is 0 and one when CNT = ARR. I want the interrupt to be triggered only once, when CNT = 0. Is it possible to do that ?

With cr1.cms = 2 and TIM1_CC interrupt, the interrupt will trigger only once in a cycle, but that time I cannot update CCR. My limitation is I can only udpate CCR when CNT is 0, and I cannot afford interrupt firing again at CNT = ARR (CNT = ARR is irrelavant as nothing is done at this event), due to performance degradation. Please help.

Thanks

[waclawek.jan · Accepted solution]

> the interrupt is triggered twice in each cycle, one when the CNT is 0 and one when CNT = ARR. I want the interrupt to be triggered only once, when CNT = 0. Is it possible to do that ?

No, this is how the Update interrupt behaves in the centre-aligned modes.

> With cr1.cms = 2 and TIM1_CC interrupt, the interrupt will trigger only once in a cycle, but that time I cannot update CCR.

Set up a *different* channel of the same timer to output compare, without actually mapping it onto a pin; set its CCRx = 0 and enable interrupt on that channel.

JW

[MMeva.1]

Thanks for the clear answer and also for the alternative. I believe that should solve my problem.

[TDK]

If the timer has one (which TIM1 does) you can set RCR to 1 to get an update event/interrupt on 0 but not ARR.

[MMeva.1]

Hello TDK,

Your suggestion also works, thanks a lot !!