Is it possible to generate a signal that indicates sampling time of a ADC externally.

[MStee.1]

Hi everyone

I have a system that uses a STM32F205 to sample on a signal at 2MHz. I wanna generate a signal that indicates the sampling times of the ADC as im battling with some frequency differences in my system. Interrupts are sadly not an option as it is used for the data acquisition and external communication. DMA requests from the main ADC isnt an option either as it is being used to aquire data and AFAIK it isnt possible to generate seperate DMA requests from a single peripherial.

My current plan and what i have been working on is setting up an identical ADC that doesnt save the sampled data but instead uses its DMA request to initiate a double buffer DMA transfer to a GPIO register. This would ideally generate a signal that switches at each sample.

My questions are:

• Is my method even possible?
  • I havent seen any reason for it not to be but it seems like a unorthodox DMA setup so im not sure.
• Is there a better mothod for generating this test signal

[waclawek.jan]

If you trigger ADC from timer, just output PWM on one of the timer's channels.

But if the input signal is not very low impedance, you could see the moment of sampling as "dip" in the signal, observing it using oscilloscope.

JW

[MStee.1]

I do trigger the adc with a timer but only the start of the sequence. From the initial timer trigger the adc is in free running mode tuned to a sampling time of 2MHz through the clock tree.

Havent been able to observe sampling time on the oscilloscope as there is other noise in the signal obscuring it.

[TDK]

> Is my method even possible?

There's no way to have a signal go high at the start of sampling and go low immediately at the end of sampling, without any overhead.

> Is there a better mothod for generating this test signal

I would simply rely on the sampling and conversion timings as indicated in the datasheet and reference manual. Do you doubt them?

[MStee.1]

I dont doubt them per say but i doubt my implementation of them.

As seen in the attached picture i get noise at the ends of my signal but not in the middle. This is despite the measured noise being uniform switching noise that persists throughout the signal. My current hypothesis is therefore that the ADC and the Timers are running at slightly different frequencies as this pattern persists over multiple measurements. Ive also checked the generated timer signals and they run consistantly at the specified frequencies with very low deviation.

This is why i wanted to generate a signal that indicates the start of each ADC sample to visualize and possibly solve the problem.

[TDK]

Ah, understood.

I don't think there's a way of doing this. Not sure what else could help other than general advice on minimizing ADC noise.

https://www.st.com/resource/en/application_note/cd00211314-how-to-get-the-best-adc-accuracy-in-stm32-microcontrollers-stmicroelectronics.pdf

The ADC clock should be divided off of PCLK2. No other option on this chip.

[waclawek.jan]

> Havent been able to observe sampling time on the oscilloscope as there is other noise in the signal obscuring it.

For a test, to see the sampling "notches", disconnect the original signal source and just ground the signal through some relatively large resistor.

JW