Is it possible to clock the STM32H7 SAI for 48/96/192 KHz output with internal oscillators?

[Mttjcksn]

Hi all,

I noticed in the SAI examples for the STM32H7 EVAL board that when selecting 48KHz for the SAI output, the actual output is only ~47.8KHz.

Looking at the code, I see the following:

/* SAI clock config:
       PLL2_VCO Input = HSE_VALUE/PLL2M = 1 Mhz
       PLL2_VCO Output = PLL2_VCO Input * PLL2N = 344 Mhz
       SAI_CLK_x = PLL2_VCO Output/PLL2P = 344/7 = 49.142 Mhz */

The datasheet recommends 98.304 MHz as the SAI input clock, because it must be divided down by a multiple of 256. 98.204MHz / 512 = 192KHz. Makes sense.

So the BSP drivers in the example used in the example get close at 49.142MHz / 128 = 191.961KHz. Close, but not correct.

I can't find any way of providing this internally, using PLLs or otherwise, and presumably neither could the engineers who wrote the BSPs.

Can anyone shed some light on how it is expected to clock at the correct frequency? I'd rather not have my peripheral clock running at an 'odd' frequency either.

Is it expected that you must use a 98.204MHz oscillator on the HSE input to get an accurate SAI clock at 48/96/192, or am I missing something obvious?

Also, I would ideally be using the clock recovery module to adjust the SAI input clock precisely. Is this possible in any way?

Thanks in advance for any suggestions,

Matt

[Mttjcksn]

Unfortunately the incoming stream could be USB, ethernet, or another peripheral, so will not have a clock.

The SAI basically needs a 98.304MHz clock in order to generate a useful master clock, so I don't think the LSI will be up to it :\

[MikeDB]

Are you sure ? The only clock that has to be accurate is the bit clock, which is 24(32)*48(96/192)kHz*num_channels which is only a few MHz. If you are driving D-A convertors, MCLK just needs to be higher than the required frequency, not exactly equal to it.

[Piranha]

That is how one can get all 44,1/48 kHz based exact audio clocks and 48 MHz for USB simultaneously from a single 24.576 or 12.288 MHz crystal. Actually only one PLL for audio clock is needed if re-configuring DIVN. And by changing DIVP a x2, x4, x8 clocks can be obtained. That would be the most typical way of doing this.

And now about original question. Here we go: