2019-03-21 11:16 AM
Hi all,
I noticed in the SAI examples for the STM32H7 EVAL board that when selecting 48KHz for the SAI output, the actual output is only ~47.8KHz.
Looking at the code, I see the following:
/* SAI clock config:
PLL2_VCO Input = HSE_VALUE/PLL2M = 1 Mhz
PLL2_VCO Output = PLL2_VCO Input * PLL2N = 344 Mhz
SAI_CLK_x = PLL2_VCO Output/PLL2P = 344/7 = 49.142 Mhz */
The datasheet recommends 98.304 MHz as the SAI input clock, because it must be divided down by a multiple of 256. 98.204MHz / 512 = 192KHz. Makes sense.
So the BSP drivers in the example used in the example get close at 49.142MHz / 128 = 191.961KHz. Close, but not correct.
I can't find any way of providing this internally, using PLLs or otherwise, and presumably neither could the engineers who wrote the BSPs.
Can anyone shed some light on how it is expected to clock at the correct frequency? I'd rather not have my peripheral clock running at an 'odd' frequency either.
Is it expected that you must use a 98.204MHz oscillator on the HSE input to get an accurate SAI clock at 48/96/192, or am I missing something obvious?
Also, I would ideally be using the clock recovery module to adjust the SAI input clock precisely. Is this possible in any way?
Thanks in advance for any suggestions,
Matt
2019-03-21 12:41 PM
What do you mean "internally"? By using HSI? Have you read HSI specification in DS?
JW
2019-03-21 12:58 PM
Thanks for the reply JW,
By internally I mean with internal oscillators - so the HSI, CSI, RC48, and the use of any PLLs.
I have read the RCC, SAI, and various other sections of the datasheet, and used CubeMx to try to find a solution.
Many thanks
Matt
2019-03-21 02:19 PM
HSI's error according to DS is around 0.5%, that corresponds to your finding.
JW
2019-03-22 01:00 AM
Hi JW,
Well it may be the case that it's pointless even trying to achieve exactly 48k because the oscillator isn't accurate enough, but that wasnt really the point of my question. Is it possible to configure the chip for 48k SAI output using internal oscillators?
Given the HSI error margin, my second question is even more important: is it possible in any way to clock the SAI from the clock recovery module? It doesn't appear to be from the datasheet, but I may have missed something.
Many thanks
2019-03-22 01:13 PM
I don't use the 'H7 but from reading the RM, its PLLs are fractional, so I assume you can get fairly close to any target frequency, of course at the cost of any jitter increase introduced by the fractional PLL.
The Clock recovery system (CRS) is not a clock source itself, but it's an automatic trim on the HSI48 - in fact it's sort of a complex and slow PLL locking the HSI48 to USB SOF or LSE - so if you use the HSI48 as the primary clock source for the PLL which generates the SAI clock, then the answer is yes.
Upon closer reading of RM0433, HSI48 can be used to clock only the USB modules and RNG, so the answer is no.
JW
2019-03-22 04:12 PM
Are you connecting this to master digital audio controllers ? In which case it doesn't matter as the SAIs will slave to the clock from that. And if your H7 is the master (as mine is) the best bet is to have a separate extremely low jitter external oscillator for the audio frequencies that can be tuned precisely.
2019-03-23 04:45 AM
Thanks JW, that is the conclusion I came to as well.. Unfortunately there doesn't seem to be a solution, was hoping I had missed something..
2019-03-23 04:49 AM
Hi mbryant,
The system will be receiving a data stream, processing the data, and transmitting over SAI with a master clock. I need to adjust the SAI clock to accommodate for drift in the incoming stream.
Hope that makes sense...
2019-03-23 04:54 AM
Surely unless you do sample rate conversion then the SAI output has to be at the data stream input freq so you just slave the SAI output off of the input clock ?
However I did think afterwards, there is the 32kHz LSI clock. If that can be routed to the SAI PLL and multiplied by three you'd get a 96kHz output which most audio stuff can take nowadays.