PCB layout for oscillator - separated GND plane confusion

[freeflyer]

I am designing a 4 layer PCB which uses an STM32L433 and working on the layout for the LSE and HSE crystals. 

I referred to the application note AN2867 for guidance, but I am confused by the isolated ground plane underneath the crystals as shown in Figure 14...

https://www.st.com/resource/en/application_note/an2867-guidelines-for-oscillator-design-on-stm8afals-and-stm32-mcusmpus-stmicroelectronics.pdf

1. How is the isolated ground plane supposed to be connected to the ground net ?

2. Do all inner layers need an isolated ground plane ?

At the moment, the isolated ground plane is only on inner layer 1 and its ground connection is made by the vias on the guard rail to inner layer 2.

Below are screenshots of the current implementation.

The screenshot below shows the top layer (signals in red) and inner 1 layer (ground in green)....

The screenshot below shows the top layer (signals in red) and inner 2 layer (ground in orange)....

The screenshot below shows the top layer (signals in red) and bottom layer (signals in blue)....

[Mikk Leini]

Technically you should connect the oscillator circuit ground connection close to the current source (MCU Xtal out pin) to have smallest possible current loop, but the closest MCU ground pin is not near Xtal pins, it's many pins away and that's probably a power ground pin (VSS). So not very ideal solution.

Well, it's only personal advice, but the way how I have interpreted the isolation requirement is that the area around and below oscillator circuit should be isolated from noise. So no other circuit ground currents should flow through that part of the circuit. It can be achieved like application note says - leave a gap with main ground, but that creates other issues. Yet if you manage to keep oscillator area noise free then you can use same solid ground plane for MCU and oscillator. You just need to judge based on the rest of the design. 

[AScha.3]

> 1. How is the isolated ground plane supposed to be connected to the ground net ?

1. Always it has to be connected to GND !

2. deeper sense of the isolated/separated area in gnd plane is: to avoid any current or voltage spikes disturbing the small analog signal at the crystal.

But this has to be connected to ground (chip ground), perfect if there is a "gnd" pin only for this - but if you have a package without so many gnd pins, use the closest/shortest next gnd pin to connect the crystal-gnd-area;

or if no pin close , just connect to gnd plane at/under cpu.

see from an2867: i made green arrow

> 2. Do all inner layers need an isolated ground plane ? no. Just at the crystal to avoid any stray in.

3. Dont connect the cap here - you couple the noise on 3v3 to the crystal-gnd , thats much worse than anything else !  Even no separate ground area and just a continuous gnd  plane would be better !

Nothing has to have any contact to this small ground area, except in one point at/close the cpu !!!!

[gbm]

From my experience: in order for LSI to oscillate on STM32L4, do not place ANY plane under it and avoid PCB traces running in parallel to its connections on the bottom side.

Also, the LSI and HSI traces should go through capacitors to the crystals (so put capacitors closer to MCU than the crystals.

[LCE]

The GND "isolation" definitely only refers to the outer layer where the crystal is placed, so that there is a "guard ring" around the crystal, as the picture also says.

As the others say, it would be nice to connect this guard ring only to the MCU's internal oscillator's GND pin, but too often it's simply not possible.

I'd say where the crystal caps are exactly placed doesn't matter, as long as all components are as close as possible to the MCU pins.