Independent Dead-time for Advanced Timer

[Vivek Sankaranarayanan]

Posted on July 21, 2017 at 01:50

Hi All,

I'm using the advanced timer TIM1 on STM32303VC to drive a 2 phase shifted full bridges separated by a transformer (Dual Active Bridge topology). This required use of 4 PWMs. CH1 and CH1N drive the primary bridge. CH3 and CH3N drive the secondary bridge.

The question is I need to program independent dead times (for CH1-CH1N and CH3-CH3N). Is that possible? Because the LL APIs have only one dead time configuration value per Timer.

If it's not possible what is the workaround? This is a make or break situation for my converter.

Regards,

Vivek

#phase-shift #advanced-timers #timer-synchronization

[waclawek.jan · Accepted solution]

Posted on July 21, 2017 at 10:53

The question is I need to program independent dead times (for CH1-CH1N and CH3-CH3N). Is that possible?

No.

If it's not possible what is the workaround?

Using two different timers?

JW

[Vivek Sankaranarayanan]

Posted on July 21, 2017 at 14:27

 Thanks JW.

Can I apply phase shift if I drive the bridges using two different timers? Also I need to apply this work around in my existing hardware.  So that means I can configure Tim1_ch3-ch3n as input high impedance and short it with Tim8_ch1-ch1n. That should work right?

[Asantos]

Posted on July 25, 2017 at 01:04

Vivek,

    The STM32F334 has the HRTIM with an independent deadtime control for each channel. 

    Why your phase shift bridge need independent deadtime?

  Ari.

[Vivek Sankaranarayanan]

Posted on July 25, 2017 at 01:39 The original post was too long to process during our migration. Please click on the provided URL to read the original post. https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I6sA&d=%2Fa%2F0X0000000bx2%2FMBa0Pb13GfzSCieP2HHzKgLR4druZwnSwub1ujIHMz0&asPdf=false

[waclawek.jan]

Posted on July 25, 2017 at 10:58

Thanks for sharing your solution.

The reference manual mentions resynchronization delay but it never mentions what value will this resync. delay be.

Good question; I've never seen the inter-timer TRGO-TRGI delay properly specified - maybe in some of the appnotes?. TIMx_SMCR.MSM bit description vaguely hints about delaying the effect of TRGI ' to allow a perfect synchronization between the current timer and its slaves'; I've never tried that either.

JW